methodology size 中文意思是什麼

methodology size 解釋
方法大小
  • methodology : n. 方法學，方法論；研究法；【生物學】分類法。adj. -logical
  • size : n 1 大小，尺寸規模身材。2 （鞋帽等的）尺碼，號；（紙張的）開。3 巨大，大量；相當大的分量。4 〈口...
  1. The methodology developed here includes promising avenues for future launch vehicles of still bigger size or more exotic designer.

    這里所陳述的方法還對未來的更大尺寸或特異設計的發射區飛行器也提供了一些有希望的解決途徑。
  2. Population index ? covers all fields of interest to demographers, including fertility, mortality, population size and growth, migration, muptiality and the family, and research methodology

    人口索引向人口學家，包含死亡人數，人口數量和成長，遷移，結婚率和家庭的研究方法覆蓋所有的使人感興趣的領域。
  3. Firstly in this part, computer simulation methodology based on the baecher model for generating network of discrete fractures was presented, which includes the follow details : probability distributions of fracture density, orientation, trace length, size, and aperture and estimation of their statistical parameters ; stochastic models of fracture network ; monte - carlo ' s simulation method ; numerical simulation procedure and technicality. then, boundary element method was used to calculate flow through the generated fractured network. assuming single fracture as a two - dimension inexpressible isotropic porous media, boundary element method equations for flow in single fracture and then in fracture network were derived using the weighted residual method

    給出了離散裂隙網路模型所依據的基本假定；發展了基於baecher模型的離散裂隙網路計算機隨機生成技術：詳細地推導了單裂隙滲流和多裂隙相交網路滲流的邊界單元法公式，發展了離散裂隙網路中穩態滲流的邊界元數值技術，並且討論了相關的具體數值技術細節，如角點的處理方法，單元的自動剖分等：描述了混合邊界元?管流模擬方法及其數值實現；研究了裂隙網路的簡化方法，並針對裂隙網路邊界元法的特點提出了一種改進的分塊三角分解法。
  4. The methodology adopted by most existing cam / cnc systems, which uses huge amount of linear segments to approach the original shape and make linear interposition increases the cost of memory size and communication work of the cnc system tremendously. a new approach based on cubic polynomial and b spline interposition to rebuild the cam generated tool path under real time condition is presented in the paper. applications on cnc machine tools showed that the presented approach improves the machining accuracy and increases the cutting speed significantly

    目前大多數cam / cnc系統採用大量小直線段逼近原始曲線和直線插補的做法，只能獲得零階連續的走刀軌跡，逼近精度低，不能保證高速加工運動的平穩性，因而加工精度、光潔度和加工速度都難以提高；由小直線段構成的nc代碼數據量龐大，也增加了數控系統在內存容量和數據傳輸方面的成本。
  5. This paper, based on collecting many empirical determinations of strength parameter for jointed rock masses all over the world, puts forward the improved empirical determination of strength parameters, that is to say, " size effect reduction factor " and " jointed rock reduction factor " of the intact rock specimen for the study on jointed rock mass strength parameter, and applies to the a typical location of the dam, which proves that this methodology is feasible and rational, and a new way for study of strength parameter in jointed rock masses is established

    在大量收集國內外節理巖體強度參數經驗確定方法的基礎之上，提出了改進的節理巖體強度參數經驗的確定方法，即對完整巖石進行「尺寸效應折減」與「節理化折減」的二次折減法，並應用於某壩址區工程實例中，所得的計算值與現場實測抗壓強度值接近，較以往的經驗確定方法更加準確，證明了節理巖體強度的降低是尺寸效應與節理化綜合作用的結果，為節理巖體強度參數的研究提供了一條新的思路。
  6. In this thesis, we first introduce the methodology of combinatorial design of testing parameters and the effectiveness of pairwise testing. then we define pair - combinatorial graph ( pcg ) and case sub graph ( csg ) to analyze the pair - cover problem and indicate that to achieve a minimum test set for pairwise testing is an npc problem, but the size of such test set is in a predictable range

    本文首先介紹基於參數組合的測試設計方法和配對覆蓋測試方法的有效性，並提出配對組合圖（ pair - combinatorialgraph ， pcg ）和案例子圖（ casesubgraph ， csg ）的概念來描述配對覆蓋問題。
  7. Similar with design verification problem, to predigest chip level layout synthesis problem, the layout synthesis based on the standard - cell methodology can be divided into two levels : inner standard - cell and among standard - cells. however, along with the increasing of chip size, chip level layout synthesis problem become more complex if it still bases on general manual standard - cell. because the router cannot impose the characteristic of the transistors in the standard - cell, it may reduce the performance of the whole chip

    通常，基於標準單元布圖模式將版圖綜合劃分成單元內與單元間兩個層次，以簡化晶元級自動版圖綜合問題的復雜性；但隨著晶元規模的不斷擴大，基於主要以手工定製的小規模標準單元，晶元級版圖綜合問題的復雜性不斷增大，且標準單元間布線無法充分利用單元內晶體管特徵，影響晶元的整體性能。
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