mixed logic 中文意思是什麼

mixed logic 解釋
混合邏輯
  • mixed : adj 1 混成的，混合的。2 混雜的，各式各樣的。3 男女混合（成）的；各階層混合成的。4 〈英國〉男女同...
  • logic : n. 1. 邏輯，理論學。2. 推理[方法]；邏輯性，條理性。3. 威力，壓力，強制（力）。
  1. Abstract : the basic theory and function of cd retrieval and systemic constitution of multimedia searching databases cd co - developed by the author and tsinghua university is stated. the system consists of load, databases, html browser, editing and print. the system almost holds out multimedia format and has powerful retrieving function, it not only involves all methods of manual retrieval, but also carries out logic and mixed retrievals. the process in fact is one during which data are matched. the result shows : cd databases make retrieving popularized, simplified and have vast foreground in storage

    文摘:介紹了作者與清華大學合作開發的多媒體全文檢索數據庫光盤的系統組成與光盤的檢索功能及原理.系統由標引系統、資料建庫系統、超文本瀏覽器、編輯出版系統組成.該系統幾乎支持所有的多媒體格式，具有強大的檢索功能，不僅囊括了手工檢索的全部方法，還可進行模糊邏輯檢索和任意混合檢索.其檢索過程實際是一個數據匹配的過程.實踐證明，光盤數據庫使檢索大眾化、簡單化和普及化，在信息儲存方面前景廣闊
  2. Predictive control for hybrid system based on mixed logic dynamic model

    基於混合邏輯動態模型的混雜系統預測控制
  3. The author is absorbed in research on technology of coprocessor design. in the floating - point addition the paper proposes a carry chain of dynamic and static mixed circuits and a good balance between speed and area of predicting leading - zero logic circuits, considering algorithm and construction of logic circuits. an approach of micro program controller design for coprocessor is put forward and a test bench is given to verify its function

    筆者研究協處理器的設計技術，在浮點加法器中提出動態與靜態結合設計進位鏈的方案以及前導零預測面積與速度的折衷方法；在微程序控制器的設計中提出一種協處理器微程序控制器的設計方法，並且給出其功能驗證的測試平臺。
  4. Logic memory mixed design

    邏輯記憶混合設計
  5. Circuit design is the basis of design of demultiplexer. speed, power and chip area are the main factors that should be considered in circuit design. every circuit structure has its merits and drawbacks, e. g. cmos logic family has a slower speed, but lower power, smaller area, scfl ( source couple fet logic ) family has a higher speed, but higher power, larger area. we should choose a proper circuit structure or their mixed structure for certain design to get a good tradeoff among the three factors. flip - flop is the fundamental element of demultiplexer, setup time and hold up time are key factors, which influence the speed of circuit, thus the design aim is how to reduce them. in this thesis we place emphasis on the design of scfl latches

    速度、功耗、面積是電路設計要考慮的主要因素，不同的電路形式具有不同的優缺點，如cmos互補邏輯電路功耗低，面積小，速度相對較慢； scfl （源極耦合fet邏輯）電路速度高，功耗和面積較大。所以要針對具體設計需要選用適當的電路形式或其組合結構，以滿足設計要求。觸發器是分接器的基本組成單元，建立時間和保持時間是影響電路速度的關鍵，所以減小建立時間和保持時間是觸發器設計的主要目標，本文著重介紹了scfl鎖存器的設計和優化方法。
  6. Moving horizon state feedback predictive control for hybrid system based on mixed logic dynamic

    混雜系統滾動時域狀態反饋預測控制研究與實現
  7. Abstract : an efficient partitioning algorithm for mixed - mode placement, extended - mffc - based partitioning, is presented. it combines the bottom - up clustering and the top - down partitioning together. to do this, designers can not only cluster cells considering logic dependency but also partition them aiming at min - cut. experimental results show that extended - mffc - based partitioning performs well in mixed - mode placement with big pre - designed blocks. by comparison with the famous partitioning package hmetis, this partitioning proves its remarkable function in mixed - mode placement

    文摘:提出一種專用於帶有預設計模塊的混合模式布局的劃分演算法.它基於擴展的mffc結群演算法，結合自下而上的結群和自上而下的劃分為一體進行混和模式下的劃分.這樣不僅可以使劃分能夠考慮電路本身的邏輯依賴，而且可以得到很好的"最小割"劃分結果.實驗結果表明，這種劃分演算法在層次式混合模式布局流程里起到了顯著的作用.將此演算法和當今國際上著名的劃分包hmetis進行比較，結果表明此演算法有一定的優勢
  8. The mixed - signal oscilloscopes, with 2 analog channels and 16 digital channels, uniquely combine the detailed signal analysis of a scope with the multichannel timing measurements of a logic analyzer

    這些多功能示波器具2個示波器通道和16個邏輯定時通道，它們把示波器對信號的詳盡分析與邏輯分析儀的
分享友人
分享到 Line

分享到臉書