module logic 中文意思是什麼
module logic
解釋
模塊邏輯-
This paper mainly aims at the characteristics of the hardware and software structure of the parallel computer on satellite, and has fulfilled researches of fault tolerant technique in three aspects of control theories and engineering : the first research of the system level fault - tolerant module is based on the system structure of the parallel computer on satellite, a kind of cold backup module and a kind of hot backup module for multiprocessor computer have been put forward. then the research of software fault tolerant technique which is based on the operate system named rtems has been carried, the mission level fault - tolerate arithmetic and the system level fault - tolerate mechanism and strategies based on the check point technique have been put forward, at the same time the self - repair technique of software which has used the technique of system re - inject has been studied. finally the technique of components level fault - tolerant based on fpga has been studied, a kind of two level fault - tolerant project which aims at the fault - tolerant module of the parallel computer on satellite has been put forward, and the augmentative of circuit that project design realization need is little, this project can avoid any breakdown of any part logic circuit of the fpga
本課題主要針對星載并行計算機體系結構及軟體結構的特點，從如下三個方面進行了容錯控制理論研究和實踐工作:首先進行了基於星載多cpu并行計算機體系結構的系統級容錯模型研究，提出了一種多cpu冷備份容錯模型和一種多cpu熱備份容錯模型;然後進行了基於rtems操作系統的軟體容錯技術研究，提出了任務級容錯調度演算法以及基於檢查點技術的系統級容錯恢復機制和策略，同時研究了利用系統重注入進行軟體在線自修復的容錯技術;最後研究了基於fpga的部件級容錯技術，提出了對容錯模塊這一星載并行計算機關鍵部件的兩級容錯方案，實現該方案所需增加的電路少，可避免板級晶元以及fpga晶元內部任何邏輯發生單點故障。 -
These character based on sichuan power network ' s practice operation experience, in allusion to the config of the carrier wave protection in bypass breaker operating, through the study of protection ' s typical config : one side lfp - 902a, one side csl - 101a, proceeded comprehensive act module test, noted plenty of first hand test data and wave picture, proceeded detailed theory analyses, plenitude demonstration atresic type carrier wave distance protection when twain side atresic type logic is not completely same, basically can fill power network ' s requirement to relay of reliability selectivity speedly and sensitively
本文結合四川電網的實際運行經驗，針對旁路開關代路運行時的保護配置情況，通過對旁路代路時保護典型配對組合：一側lfp - 902a ，一側csl - 101a的保護配置情況的深入研究，做了全面的動模試驗，記錄了大量的第一手試驗數據和波形，進行了詳細的原理分析，充分驗證了高頻閉鎖式距離零序保護在兩側閉鎖式邏輯不盡一致的情況下，基本能夠滿足電網對繼電保護的可靠性、選擇性、快速性以及靈敏性的要求。 -
Digital image processing consume a large amount of memory and time commonly. basing on the advantage of fpga, the paper design harware module by hdl ( hardware language ), i. e., some function is achieved by les ( logic element ) of the fpga. the real - time of digital image processing is achieved by this. the sample and display of digital image is the important part. so, the paper mainly design the sample and desplay module. the sample card is designed and it ’ s word mode is configured according china ’ s cvbs ( composite video bar signal ). for acquiring the image and storing it correctly to sram, the paper design the sample - control module. the sample module can work correctly using least time. the reliability and real - time achieve the reference. according the vga principle and scheduling of the ths8134, the paper design a vga - control module by hdl. firstly, the control signal is synthesized secondly, the horirontal and vertical synchronization signals is synthesized according to the vga interface standard
圖像處理的特點是處理的數據量大，處理非常耗時，為實現數字圖像的實時處理，本文研究了在fpga上用硬體描述語言實現功能模塊的方法，通過功能模塊的硬體化，解決了視頻圖像處理的速度問題。圖像數據的正確採集和顯示輸出是其中的兩個重要的模塊，因此，本文主要完成了圖像數據的採集和顯示輸出的設計。本文設計了採集卡，並要對其工作模式進行了配置和編寫了採集控制模塊，在採集控制模塊的控制下，將數字圖像數據正確無誤的存儲到了sram中。 -
The structure includes : iicm ( input interface control module ) 、 oicm ( output interface control module ) 、 edcm ( experiment data control module ) 、 sefcm ( simulation experiment framework control module ) 、 mscm ( model structure control module ) 、 slcm ( simulation logic control module )
其中包括:輸入介面控制、輸出介面控制、實驗數據控制、模擬實驗框架控制、模型結構控制以及模擬邏輯控制。 -
The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing
本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。 -
Complete the bi - directional data communication between the hardware and the microcomputer. ( 3 ) design the cpld ( complex programable logic device ) processing circuit to preprocess the initial signal in the data acquisition module
（ 3 ）下位機採集模塊部分，在一塊cpld （ complexprogramablelogicdevice ）集成晶元上燒寫了設計的電路，能夠對輸入原始信號進行預處理。 -
Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo
本文首先對數字減影血管造影（ dsa ）成像系統的組成結構和數據流向進行了深入研究和分析，並對系統中的數據流向進行了完整的歸納和總結，給出了x線數字成像系統中的高速大容量數據通道的設計方案；在對sdram的控制方式做了深入探討后，給出了實現大容量多條sdram共同工作的解決方案，在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲；通過對pci總線介面的深入研究，優化後端狀態機設計和低層驅動程序開發，給出了完整的pci介面方案實現高速dma數據傳輸，完全可以滿足視頻傳輸要求；深入研究了基於大規模可編程器件的數字系統設計方法，針對通用fifo使能信號漂移、輸出數據難于建立和保持等設計難點，提出了利用fpga中的鎖相環提供多個時鐘相移的信號來提高系統穩定性的解決方案，從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。 -
First, based on the analysis of the design method of two - valued shift counter, we use the multivaled circuit ' s property of high information density to put forward the design method of three - valued shift counter. by using this method module - n three - valued shift counter can be designed. and by selecting the best design method, the simplest circuit of control logic can be made
首先，在分析二值的移位計數器的設計方法的基礎上，利用多值電路的高信息密度，提出了三值移位計數器的設計，運用該方法可以設計任意狀態的三值移位計數器，並且通過選擇最佳設計方案使控制邏輯電路最簡。 -
If all errors belong to single or multiple temporary 0 1 - error or stuck - at - error produced by one module, then these errors can be corrected effectively. the results obtained from the simulation validate the correctness of the cl - acl structure. analytic results show that the delay of the cl - acl structure is dramatically less than that of a dmr structure using alternating - complementary logic mode
這些粒子所引起的干擾不僅將改變存儲單元的邏輯值，而且將導致邏輯電路產生瞬時輸出脈沖，如果這些脈沖在某個關鍵的時間段里產生，比如在時鐘或數據的變化過程中，那麼它們將間接地使其它電路的狀態產生變化。 -
This thesis focuses on the ingress process module of ctu, which translates c - 5 dcp format to rainier 4gs3. the specification analysis, architecture and logic design, functional simulation testbench design, synthesis report and testing result are discussed in this thesis. the research work mainly includes : the specification analysis and design requirements of ctu logic ; the architecture and logical design of ingress process module, which includes receive control fsm, send control fsm and cell position adjustment logic ; the performance improvement of ingress process module to receive and transmit data cell at the full line speed
本論文的主要研究工作包括：通信協議轉換邏輯的功能分析和設計需求；通信協議轉換邏輯上行方向的系統分析及體系結構設計，包括上行接收狀態機、發送狀態機、信元內位元組位置調整機制等的設計；通信協議轉換邏輯上行方向的線速設計，主要是上行接收的線速設計，要使用流水設計技術；提出了高速實現roundrobin調度策略的實現方法，並設計實現了桶式移位器和優先級編碼電路；應用bfm模擬模型設計了上行處理各模塊的模擬testbench ，完成了各級模塊的模塊模擬和系統集成模擬。 -
Each logic module was verified by simulation
通過模擬，驗證了各個模塊邏輯設計的正確性。 -
The trigger electronic module consists of 3 discriminators and a coincidence unit which performs a 2 - out - of - 3 logic gate. hence either 2 detectors or 3 detectors receiving cosmic ray signal will trigger daq
觸發電路模組由三個鑒別器和一個與門電路組成。當有兩塊或以上的探測器同時產生訊號，該電路便會觸發數據收集。 -
Finally the module is accomplished successfully after installation and debugging. it mainly consists of the minimum system of dsp, a / d conversion circuit, cpld control logic, watchdog circuit, op amplifier and filter circuit
該模塊主要由數字信號處理器最小系統、模數轉換電路、復雜可編程邏輯器件控制邏輯、看門狗電路、運算放大器電路和模擬濾波器電路構成。 -
In the process of implementation, it is essential to find a scheme to solve the following problems : ( identification of the logic channel type of signals from handsets, which is the key to determine which decoding module should be called
本論文的主要任務是用dsp ，通過幾個模塊之間的聯調，實現基帶處理的接收模塊的功能。接收模塊主要完成gmsk解調和解碼功能，並將所解碼出的手機上行的信號傳遞給信令模塊。 -
Soa is the new principle used as logic module in the computer program ( named as services ), which can be thought as a guidance of design, exploitation, deployment, arrangement of the logic module, and it can form a proper way to build application program, organize the it fundamental infrastructure and operation function. although soa is often linked with xml and web services technology, the latter is usually nothing more than regarded as the technical realization of the soa principle in allusion to the real application surroundings
Soa只是設計、開發、部署和管理網路中計算機程序邏輯（稱作為「服務」 ）具體模塊的方法的最新規范原則，它是構成應用程序、組織it基礎設施和業務功能標準化的一種方法。雖然soa常常與xml和webservices連在一起，但後者只是soa原則針對具體應用環境的技術實現。 -
In the constructing of the diagnosis module using the technology of the combination of the fuzzy logic and neural network, which based on the fuzzy adaptive learning control network, a simple kind of capable method for consummate the structure and performance of network is introduced, which includes the rules extraction based on the maximum weights matrix and the parameters amendment based on genetic algorithm by floating - point coding. during the monitoring of the parts condition, the output of the condition monitoring system shows the good working condition of the executing agency by fuzzily deducing from the control instruction send by the auv ' s controller and motion status, and so offers the proof to complete mission and return safely
在珍斷模塊建模中採用模糊邏輯與神經網路結合的技術，以模糊自適應學習控制網路為核心，提出了一種簡單可行的基於最大權值矩陣的規則提取及基於浮點數編碼的遺傳演算法的參數調整的，完善網路結構與性能的方法，並在狀態監測過程中，通過對由控制器輸入的水下機器人運動控制量以及運行狀態的模糊推理，得到執行部件（推進器或舵）的工作狀態優劣程度，為保證水下機器人完成任務，安全返回提供控制依據。 -
The system selects micro control unit and programmable logic device as the core of controller, gsm terminal module as communication device, gps as position equipment, a / d sampling for voltage and current checking, solar battery as power supply, switch dc - dc as power voltage conversion, and so on
以微處理單元與可編程邏輯器件為核心搭建系統控制器，選擇gsm無線通信模塊實現系統通信，全球定位系統實現水標燈定位， a d采樣與轉換實現電壓電流檢測，太陽能電池為系統供電，開關型dc - dc實現電源電壓轉換。 -
Researched the methods to test configrable logic block ( clb ) and its sub - blocks. based on a “ divide and conquer ” methodology, the clb resources are divided into three basic blocks : logic units, carry logic module ( clm ) and lut ’ s ( look up tables ) ram - mode. the testing configurations are implemented based on a two - dimensional array structure for logic blocks
主要基於「分治法」對clb及其子模塊進位邏輯（ clm ） 、查找表（ lut ）的ram工作模式等進行了測試劃分，分別實現了以「一維陣列」為基礎的測試配置和測試向量，以較少了測試編程次數完成了所有clb資源的測試。 -
There are six sub - modules in it : single - chip unit, data transfer unit, parallel data transfer / receive unit, serial data transfer / receive unit, system reset management and system power unit. this paper studies the design and realization of net interface module, mainly discusses design of data transfer unit ' s logic and the improvement of single - chip unit ' s software
論文首先從系統設計思想出發，對網路介面模塊的總體設計實現進行了研究，接著對作者主要研究的軟硬體分工協同設計中的軟體完善部分，邏輯設計部分，以及最後的邏輯測試、系統測試進行了重點論述。 -
This thesis mainly introduce a development process of mis of steel tube enterprise producing. a universal mis of adapting to our country middle and small producing enterprise is developed in accordance with the practical situations of our country producing enterprise. the structure and developing method of the mis are analyzed, followed by the introduction of the development process in stages. the system development abides strictly by the requirements of software engineering, with all the files standard and complete. during the process of the development, we took into consideration practicality as well as scientific principles. the system is development under a quick prototype method. first, the logic module of the system is established through the analysis of the business flow process and the information flow concerning productive enterprise of steel tube ; secondly, in light of the module, the system is set up including the design of the system ' s network platform, developing tools, database, system code, software modules, system security, user ' s interface and so on. finally, the prototype of the system is implemented on the basis of the design
文中首先分析了管理信息系統的開發方法和體系結構，然後分階段地介紹了具體的開發過程。該系統的開發嚴格遵守軟體工程的要求，文檔規范完善，在開發過程中堅持實用性和科學性相結合的原則。系統採用快速原型法進行開發，首先通過對鋼管生產企業業務流程和數據流程的分析，建立了系統的邏輯模型；接著針對該模型進行系統設計，包括對系統的網路平臺、開發工具、數據庫、編碼、軟體模塊、系統安全及用戶界面等方面的設計；然後在設計的基礎上實現了系統原型；通過對原型的評價和改進，使原型最終成為實際產品。
分享友人