mos integrated circuit 中文意思是什麼

mos integrated circuit 解釋
mos集成電路
  • mos : 不需要現場收音的無聲取景
  • integrated : adj. 完整的，完全的。 an integrated iron and steel works 鋼鐵聯合企業。 an integrated oil company 大型石油（聯合）公司。
  • circuit : n 1 （某一范圍的）周邊一圈；巡迴，周遊；巡迴路線[區域]；迂路。2 巡迴審判（區）；巡迴律師會。3 【...
  1. Complementary mos integrated circuit comos - ic

    互補金屬氧化物半導體集成電路
  2. Complementary mos integrated circuit comos - i

    互補金屬氧化物半導體集成電路
  3. The macro model of drift region resistance was established based on the solution of poisson ’ s equations and continuity equations. by the combination of spice mos ( level = 3 ) and the macro model, the complete dddmos model was then obtained, which accords well with simulated data. by simulating and comparing different devices of different process parameters, the model is applicable for different bias regions and can be useful in the power integrated circuit research in future

    首先介紹了器件建模的基本原理及相關模擬技術，然後利用工藝模擬軟體生成器件基本結構，並對其基本特性進行了分析;分析了業內和學術界比較通用的高壓器件建模的方法，隨后在模擬實驗的基礎上著重分析了dddmos的物理特性，在求解泊松方程、連續性方程等基本方程的基礎上，建立有物理意義的漂移區電阻的宏模型;隨后結合spicemos （ level = 3 ）模型而得到完整的dddmos模型，此模型與模擬數據符合得比較好，通過對不同工藝參數的器件進行模擬比較，該模型能夠覆蓋不同的工作偏壓范圍，具有較明確的物理意義，對今後的功率集成電路的研發有一定的參考意義。
  4. Xing su ( microelectronics and solid state electronics ) directed by prof. lin chenlu the fast development of information technology requires integrated circuit to be greater integrated, faster functioned, and lower power - consumed, that lead to continuous shrinkage of mos and dram feature size. and under this trend the thickness of mos gate dielectrics ( sio2 ) would soon scale down to its physical limit

    日益增長的信息技術對更高集成度、高速、低功耗集成電路的需求，驅使晶體管的尺寸越來越小，隨之而來的問題是作為mos柵氧化物和dram電容介質的sio _ 2迅速減薄，直逼其物理極限。
  5. After introduction of the tranlinear loop principal, the bjt current controlled conveyor has been designed by using mixed tranlinear loop voltage follower. as for modern integrated circuit, the model of mos transistor, the active resistance and the current mirror integrated circuit formed by mos transistor are introduced. the cmos current controlled conveyor has been derived from mixed tranlinear loop cmos voltage follower based on weak inversion operation

    針對現代集成電路的工藝，本文對mos晶體管的工作原理進行了簡要的敘述，討論了有源電阻和電流鏡的實現方法，並利用mos晶體管的亞閾值特性組成混合跨導線性迴路完成對應的電壓跟隨器的設計，推導出了基於cmos技術的電流控制傳送器。
  6. In this paper, a three phases high - voltage power mos gate drive integrated circuit has been researched and designed successfully. it is a typical spic, which could be widely used in high power motor control and switching power supply applications. the design goal of the circuit are v0ffset ( max ) is 500v, ia ( m ~ ) is 1 a, the highest frequency of operation ( f ( ~ x ) ) is 100khz

    本文研製成功了一種可廣泛用於大功率電機控制、開關電源等應用中的spic電路?三相高壓功率mos柵驅動集成電路，其設計指標要求為：最高偏置電壓（ voffset （ max ） ）為500v 、最大輸出電流（ i _ o （ max ） ）為1a 、最高工作頻率為100khz 。
  7. Edri has successively cooperate with famous foreign design company or separately designed shanghai huahong nec 909 project, tianjin motorola mos - 17 project, shanghai beiling, shanghai advanced semiconductor, beijing smic, shanghai tsmc, suzhou hejian, leshan phoenix, shenzhen si, shanghai smic fab 8, fab 9, and fab 10, green mountain integrated of nantong, wuxi hynix, changzhou nanotech, etc. dominant integrate circuit project design

    Edri先後與國外設計公司聯合或自主設計了上海華虹nec 909工程天津摩托羅拉mos - 17項目上海貝嶺上海先進北京中芯上海松江臺積電蘇州和艦無錫上華樂山菲尼克斯沈陽稀科深圳深愛上海中芯fab8 fab9 fab10南通綠山無錫hynix常州納科等國內重大集成電路工程設計。
  8. Spic ( smart power integrated circuit ) based on new power mos device develop rapidly along with the advancement of micro - electronics technology

    隨著微電子技術的進步，以新型功率mos器件為基礎的智能功率集成電路（ spic ）得到了迅速發展。
  9. Since metal - oxide - semiconductor ( mos ) device appeared, integration of integrated circuit ( ic ) expands as moore law. meanwhile the dimension of device scales down, the thickness of sio2 gate dielectric shrinks as the same law. but as the thickness of sio2 gate dielectric reaches at isa, the gate current rises very quickly and reaches at 1 10a / cm2

    自從金屬-氧化物-半導體（ mos ）器件出現以來，集成電路的集成度按照摩爾定律增加，相應地，器件的物理尺寸按照等比縮小的原則不斷縮小， sio _ 2作為柵介質的厚度不斷縮小，特徵尺寸在0 . 1 m以下的集成電路要求sio _ 2柵介質的厚度小於1 . 7nm 。
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