multiplier-divider 中文意思是什麼
multiplier-divider
解釋
乘除裝置- multiplier : n. 1. 增加者,增殖者,繁殖者。2. 【數學】乘數；【電學】倍增器,擴程器,增效器,倍率器。3. 【經濟學】收益增值率。
- divider : n. 1. 劃分者；分割者；分裂者，離間者。2. 間隔物；分裂的原因。3. （割禾機等的）分切器；【數學】除數；除法器；【電學】分壓器；【航空】減速器。4. 〈 pl. 〉劃規，兩腳規，分線規。
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It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ), 5 - stage pipeline, hardware multiplier and divider, interrupt controller, 16 - bit i / o port and a flexible memory controller. new modules can easily be added using the on - chip amba ahb / apb buses. it has flexible peripheral interfaces, so can be used as an independent processor in the board - level application or as a core in the asic design
它遵照ieee - 1745 （ sparcv8 ）的結構，針對嵌入式應用具有以下特點：採用分離的指令和數據cache （哈佛結構） ，五級流水，硬體乘法器和除法器，中斷控制器， 16位的i / o埠和靈活的內存控制器，具有較強的異常處理功能，新模塊可以輕松的通過片上的ambaahb / apb總線添加。 -
The number of error symbols that can be corrected by the decoder is 2. the design process includes storing the input data, calculating the syndromes, designing multiplier and divider and solving the key equation
Rs （ 256 ， 252 ）譯碼器的設計過程主要包括輸入數據的存儲、伴隨式的計算、乘法器和除法器的設計、關鍵方程的求解等幾個步驟。 -
Chapter 5 gives the design illumination of the rs coder and decoder based on fpga. then it gives the integrated results for realization design of the rs ( 31, 15 ) error - correcting code. after that, it gives the functional and layout simulation results for the limited field multiplier, divider, rs coder and rs de - coder
第五章給出了基於fpga實現的rs編碼器和譯碼器設計說明， rs （ 31 ， 15 ）糾錯碼設計實現的綜合結果，有限域乘法器、除法器、 rs編碼器、 rs譯碼器的功能模擬和布局布線后模擬結果，最後總結主要的調試經驗。
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