on-chip 中文意思是什麼

on-chip 解釋
片上；晶元上
  • on : adv 1 〈接觸、覆蓋〉上去；開（opp off）。 turn on the light [radio water gas] 開電燈[收音機、自來...
  • chip : n 1 碎片，削片，薄片；碎屑；薄木片；無價值的東西。2 （陶器等的）缺損（處）。3 （賭博用）籌碼；〈p...
  1. Gmc network has better high - frequency performances and is easier to control on chip than rc network

    與傳統的電阻電容結構相比，跨導電容結構有更好的高頻特性，在集成電路中較易控制。
  2. First, this paper gives a method, which is utilized by baseband system according to wcdma system capability requirements, using asic + dsp to realize raker, using dsp + dsp to realize symbol process. the hardware structure of asic + dsp and dsp + dsp is designed from the whole design view. then, the discussion is made of the main function module of ic2001 and dsp, hi module, dsp peripherals on chip such as hpi, edma and emif

    文章首先結合wcdma系統性能要求提出了基帶系統所採用的方案，由asic + dsp實現rake接收機功能和dsp + dsp實現符號級處理功能;然後從總體規劃的角度設計出asic + dsp和dsp + dsp系統硬體結構，對ic2001和dsp的主要功能模塊， hi模塊， dsp片上外設hpi口、 edma和emif總線作了分析，並結合基帶處理功能開發了系統驅動;最後由信號源發出測試數據進入系統，進行功能實現后輸出數據繪制出波形圖，對所設計的基帶系統驅動方案進行驗證分析。
  3. Xiaotao chang, dongrui fan, yinhe han, zhimin zhang. “ soc leakage power reduction algorithm by input vector control ”. international symposium on system - on - chip 2005 ( issoc2005 ), november 14 - 17, 2005, tampere, finland

    黃海林，范東睿等， 「嵌入式處理器中訪存部件的低功耗設計研究」 ，計算機學報， 2006年5期（ 815 ? 821 ） 。
  4. The nonlinear filtering for nbi estimate - subtract assumes that the prediction error is dominated by spread spectrum signal and the background noise power is far below spread spectrum chip power, this assumption promises the low error ratio of chip decision but may not be attainable to digitalized dsss receiver in military communication environment, and does not coincide with the principle of dsss communication that decreases bit error ratio ( ber ) depending on spread spectrum gain, not on chip power

    在干擾估計抵消濾波中，以往的非線性濾波要求干擾抵消濾波后擴頻信號功率遠大於殘余噪聲功率，進而假設碼片判決的誤碼片率基本為零，這一要求對軍用擴頻通信是不利的，而且也不符合擴頻通信利用擴頻增益降低誤碼率的原則。
  5. Two plasmids, which contain hbv specific dna fragment and hsv1 dna fragment, were amplified by solid phase two loci pcr and detected by enzymatic indicator system on a gene chip that was constructed by primer immobilization and modified with thiol group on chip surface. for building detection technology by dna chip in clinical, the virus genomes were extracted from the clinical positive samples by one - step nucleic acid extraction

    採用已建立的晶元制備方法，在該六種質粒中選擇含有hbv與hsv1兩種病毒dna序列的質粒為模板，進行同相兩重pcr ，採用晶元酶學槍測對固相兩重pcr的擴增結果進行檢測，得到良好的晶元酶學檢測結果。
  6. Now that a single chip is an entire system ( the concept of system - on - a - chip, soc ), on - chip interconnect is now one of the most challenging areas of 1c processing

    隨著系統晶元的出現，片內互連技術已成為目前集成電路設計中最具挑戰性的領域之一。
  7. The tested results were well agreed with theory values. the on - chip excess loss of the 1x4 splitter based on 1x2 mmi y branches was tested about 3. 1db, and the uniformity was about 0

    實驗測得基於1 2mmiy分叉結構的緊湊型1 4功分器，片內額外損耗約為3 . 1db ，均勻性約為0 . 4db 。
  8. Fulhua microelectronics corporation known as fameg is a fabless soc system - on - chip odm company, and seraphim, a professional electronic components distributor have entered into an agreement for seraphim to market and sell famg s full line of products in taiwan and china

    幸賀所代理的pki perkinelmer氙氣閃光燈組，已在2006年成功內建於世界知名手機大廠的3g手機中，並於同年7月在臺銷售。由於照相效果出色，深受市場好評。
  9. Fulhua microelectronics corporation known as fameg is a fabless soc system - on - chip odm company, bridging the technology and process gaps between our customers and the increasingly competitive semiconductor manufacturing service industry in the greater china region, by offering high quality product business and services business

    世界知名手機大廠已於2006年將pki perkinelmer氙氣閃光燈組內建於3g手機，並且於同年七月在臺銷售。此款手機搭配自動對焦內建氙氣閃光燈與防攝錄手震功能。
  10. And i finished the layout design, chip test of line driver and equalizer in 2. 5gbps baseband copper cable transceiver and equalizer in the 1. 5gbps sata transceiver respectively. the main improvements and innovations in this thesis are as follows : 1 、 to design an analog equalizer tuned on - chip for 2. 5gbps baseband copper cable transceiver ; 2 、 to present an adaptive equalizer for 1000base - cx transceiver ; 3 、 to present an auto - gain control amplifier used in the adaptive equalizer for the 1000base - cx transceiver ; 4 、 to present an adaptive continuous - time gm - c filter in very high frequency for the adaptive equalizer for the 1000base - cx transceiver

    論文主要的改進和創新有： 1 、設計了適用於2 . 5gbps基帶銅纜收發器系統片上可調的模擬均衡器電路； 2 、提出了一種新的適用於千兆以太網基帶銅纜收發器系統的自適應均衡器結構； 3 、設計了甚高頻自動增益控制放大器； 4 、設計了一種適用於千兆以太網基帶銅纜接收器均衡的自適應甚高頻連續時間gm - c二階帶通濾波器。
  11. It is shown that our presented circuit model was correct. secondly, on the basis of analghng the fhahon of pcd reader of contactless ic card, the softwar flow chat of cothetless ic card controller based on chip - thoing algorithin and the hardwar circuit and anenna of the reader were designed

    第二，在分析非接觸ic卡讀寫器功能的基礎上，設計基於時間片演算法的非接觸ic卡控制器軟體流程圖和讀寫器硬體電路以及非接觸ic卡讀卡器的天線。
  12. It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ), 5 - stage pipeline, hardware multiplier and divider, interrupt controller, 16 - bit i / o port and a flexible memory controller. new modules can easily be added using the on - chip amba ahb / apb buses. it has flexible peripheral interfaces, so can be used as an independent processor in the board - level application or as a core in the asic design

    它遵照ieee - 1745 （ sparcv8 ）的結構，針對嵌入式應用具有以下特點：採用分離的指令和數據cache （哈佛結構） ，五級流水，硬體乘法器和除法器，中斷控制器， 16位的i / o埠和靈活的內存控制器，具有較強的異常處理功能，新模塊可以輕松的通過片上的ambaahb / apb總線添加。
  13. The study of insert groove on chip - breaking mechanism

    刀片槽型對斷屑性能的實驗
  14. The influence of coat on chip - breaking performance of cutting tools and theoretical analysis

    塗層對刀片斷屑性能的影響及理論分析
  15. Integrated circuit design has entered into the era of system on chip ( soc ), the bus interconnect architecture of system on board have also developed into a kind of hierarchy architecture - on chip bus ( ocb )

    隨著集成電路設計進入到系統晶元（ soc ）時代，板極系統的總線互連結構也發展成為系統晶元的層次化總線體系一片上總線。
  16. With turning the scale of asic ( appl ication specified integrated circuits ) to s0c ( system on chip ), which conunon1y is composed of mcu, specified function ip cores, memory, periphery interface etc, the ip reuse techno1ogy is very important in s0c design flow, which can realize the constructions of different levels components. the approach of configurable system, method and design f1ow for udsm ( u1tra deep sub micron ) asic, logic system design using hdl 1anguage, coding style, static and dynamic verification strategy are a1so presented in chapter 2. in chapter 3 we study the vlsi - - dsp architecture design, dense computation and high speed high performance digital signal processing unit structure, which includes high speed mac components and distributed arithmetic unit

    在工程設計方法及結構化設計和高層次綜合的研究中，介紹了在深亞微米工藝條件使用的方法和asic設計流程，討論了高層次綜合的核心如何從描述推出電路構成的設計思路，針對不同目標的設計技巧討論了採用hdl語言進行邏輯系統設計的方法，給出了用vhdl語言進行代碼設計時的規范和風格，在面向soc的驗證策略討論了動態和靜態的驗證技術，提出了進行單獨模塊驗證、晶元的全功能驗證和系統軟硬體協同驗證的整體策略。
  17. According to the request of this subject, we have developed the system hardware and software for the slave device and the inspection software running on the pc. in this paper all of the followings is illustrated detailedly, such as the research on the principles of measurement and its realization, three means of water - level measurement that are separately based on photo electricity coder, pressure sensor and potentiometer ; selection of the microchip, we choose an advanced integrated soc ( system on chip ) microchip c8051f021 as the main controller ; realization of signal sampling, processing and its conversion in the mcu ; application of high precision 16 bits adc cmos chip - - ad7705 in our system, designing its interface with the microchip and relevant program ; using a trickle charge timekeeping chip ds1302 in the system which can provide time norm and designing of its i / o interface and program ; additionally, a 4 ~ 20ma current output channel to provide system check - up using ad421. in the system, ad421, ad7705 and the microchip compose spi bus ; to communicate with the master pc, here we use two ways which are separately rs232 and rs485 ; moreover, there are alarm unit, keyboard unit, power supply inspection unit and voltage norm providing unit in the system

    針對研製任務的要求，課題期間研製了下位機系統硬體和軟體，開發了上位機監控軟體，其中所作的具體工作包括：測量原理的研究和在系統中的實現，在本次設計中用三種方法來進行水位測量，分別是旋轉編碼器法、液位壓力傳感器法和可變電阻器法；主控晶元的選擇，我們選用了高集成度的混合信號系統級晶元c8051f021 ；實現了信號的採集和處理，包括信號的轉換和在單片機內的運算；高集成度16位模數轉換晶元ad7705在系統中的應用，我們完成了它與單片機的介面設計及程序編制任務；精確時鐘晶元ds1302在系統中的應用，在此，我們實現了用單片機的i o口與ds1302的連接和在軟體中對時序的模擬，該晶元的應用給整臺儀器提供了時間基準，方便了儀器的使用；另外，針對研製任務的要求，還給系統加上了一路4 20ma模擬信號電流環的輸出電路來提供系統監測，該部分的實現是通過採用ad421晶元來完成的，本設計中完成了ad421與單片機的spi介面任務，協調了它與ad7705晶元和單片機共同構成的spi總線系統的關系，並完成了程序設計；與上位機的通信介面設計，該部分通過兩種方法實現： rs232通信方式和rs485通信方式；系統設計方面還包括報警電路設計、操作鍵盤設計、電源監控電路設計、電壓基準電路的設計。
  18. The method of design of system on chip ( soc ) based on the field program gate array ( fpga ) is also introduced

    並對課題中採用的基於現場可編程門陣列（ fpga ）的片上系統（ soc ）設計方法進行了介紹。
  19. Superscalar risc microprocessor is the further development of reduced instruction set computer, it improve the instruction - level - parallism by means of adding parallel pipelining function units and dynamic on - chip scheduling. this thesis anslysises the architecture and the diversified techniques of superscalar computer

    超標量risc微處理器是精簡指令結構（ risc ）的進一步發展，它通過增加并行流水執行單元並結合片上硬體動態調度來提高指令并行度。
  20. 16 lin s, chang n, nakagawa o s. quick on - chip self - and mutual - inductance screen. in proc

    同時插入屏蔽和線網排序是一種減少耦合電容和耦合電感噪聲的有效方法。
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