parallel processing system 中文意思是什麼
parallel processing system
解釋
并行處理系統-
Expert system has many merits. it has the ability of heuristic illation, and can explain for illation and append new knowledge in the knowledge database. but it also has obvious shortcomings, such as, poor ablitity in ka ( knowledge achieve ), inefficient and incomprehensive. the artificial neural network has the ablitity of parallel processing, associative memory, distributed storage of knowledge and high robust etc. it also has perfect characteristics of self - organizing, self - adaptive, self - learning. it specializes in visualize ideation but is short of logic ideation
專家系統在故障診斷領域得到廣泛的應用，專家系統具有許多優點，能利用專家的知識進行啟發式推理，能夠解釋其推理過程，並能夠不斷地、靈活地增加新的知識。但專家系統也存在明顯的缺陷：獲取知識能力差、效率低、范圍窄。可以說專家系統長于邏輯思維缺乏形象思維。 -
Design of multi - dsp parallel processing system based on fpga
并行處理系統的設計 -
Design of an image fusion system based on dsp parallel processing
并行處理的圖像融合系統設計 -
Parallel processing for data statistics in network database system
網路數據庫系統中數據統計的并行處理 -
Chapter 4 studies scheduling algorithm of the core node to implement on single adsp2191. the result shows that a single adsp2191 chip can ’ t satisfy the bhp processing delay request and parallel processing is inevitable. chapter 5 primarily studies the core node ’ s scheduling algorithm with many dsp parallel process. details of lauc - vf scheduling algorithm analysis data flow organization and mission distribution are argued. the results of software simulation and hardware debugging indicate that many dsp parallel processing is effective and coincident with the system ’ s demand
結果表明單片adsp2191晶元不能夠滿足核心節點對bhp的實時處理要求，必須多dsp并行處理。第五章研究了核心節點調度演算法的多dsp并行處理。對多bhp批調度演算法的實現進行分析，探討了多bhp處理任務的的劃分和分配方案;多dsp間數據通信和傳輸的dma實現;最後對多處理器并行的處理時間進行模擬測試分析。 -
Describes the design and realization of partial run - time reconfigurable fpga in detail. in order to reduce the affect of the reconfiguration time on system execution time, mostly static circuit design method in logical design stage and incremental routing method in component implementation stage are proposed. the fft parallel processing algorithm is examined through vvp platform
本章詳細闡述了基於vvp平臺的多sharc功能插板的具體硬體實現，以動態重構fpga設計為核心，論述了局部動態重構fpga設計流程和方法，提出了極大靜態電路邏輯設計方法和遞增式布線方法，以達到減小動態重配置時間，提高系統運行效率的目的。 -
The paper firstly studies some basic concepts such as task distributing, remote calling, loading balance, processing synchronization and communication, distributed computing system model and parallel executing time connected to distributed parallel computing system
本文首先討論了在分散式系統中所涉及的任務分配、遠程調用、負載平衡、進程同步與進程通信以及分散式計算的系統模型等，並探討了并行計算中的一個重要的性能? ?并行執行時間。 -
After analyzing the characteristic of the parallel processing system, some problems about design missile - carrying processing system are pointed out ; network in the parallel processing system has become bottleneck and affect the performance of system, so the processing efficiency is analyzed in a multiprocessor system based on cluster - bus and some rules in designing the network in the multiprocessor system are brought out ; genetic algorithm is used for scheduling in the multiprocessor system, and a scheduling algorithm is described to suit arbitrary number of tasks, unequal task processing time, arbitrary precedence relation among tasks and arbitrary number of parallel processor, so that the schedule length will be minimized ; finally, an atr algorithm is mapped to a ring multiprocessor system, and a block diagram using dsp device is constructed. in chapter 4, the study is performed on real - time system hardware realization of atr. tms320c80 is selected as the kernel processor in multiprocessor system
為此，對一種由常用的dsp晶元組成的多處理器系統的處理器利用率進行了分析，提出了多處理器系統互連網路設計的基本原則；本章使用遺傳演算法作為實現多處理器調度的工具，提出了一種新的任務調度演算法，該演算法主要是為了解決在任務數任意、任務計算時間不相等、任務前趨關系任意、以及任務間存在通信和考慮任務存貯器要求的情況下，如何優化任務在各個處理器上的分配和執行順序，使得多處理器系統總的執行時間最小；最後對一個目標識別演算法進行了硬體實現優化分析，根據分析結果，將演算法映射到由dsp晶元組成的環形網路連接的處理器拓撲結構上，得到了多處理器系統的原理框圖。 -
Then, we give tile introduction of the theory of digital audio signal compression, the algorithm and somp accelerate algorithm for the mp3 encode and decode. ln the end, we propose a parallel processing system with two dsp to be a real - time mp3 encoder and decoder
然後，詳細介紹了數字音頻信號壓縮的原理， mp3編碼和解碼的演算法實現，並採用了一些編碼和解碼的加速演算法，最後提出了一個雙dsp并行處理系統用於實時實現mp3編碼和解碼。 -
( 3 ) based on principle analysis and simulation, the main parameters are obtained. and the hardware solution is proposed - parallel processing system with multiple dsp. ( 4 ) the design of the software used to control logic and timing is presented
（ 4 ）在硬體設計的基礎上，提出了在本系統中實現時序和邏輯控制的軟體（不包括正交波束形成演算法的實現）設計方案（包括系統中斷系統的設計和系統的bootload設計） 。 -
Application of image reconstruction technology in a parallel processing system
基於人工神經元網路的圖象重建 -
( 3 ) design a parallel processing system based on four adsp21160m chips to realize pulse compression in frequency domain
（ 3 ）設計基於4片高性能adsp21160m的緊耦合併行處理系統，以完成多波形頻域數字脈沖壓縮的全部運算工作。 -
Massively parallel processing system ( mpp ) and pc cluster provide distributed - memory environments for parallel solving the generalized eigenvalue problem
大規模并行處理系統（ mpp ）和pc機群為并行求解矩陣廣義特徵值問題提供了分散式存儲環境。 -
Parallel computing is an effective instrument. along with the developing of high - powered parallel processing system, image parallel processing technology will provide greater space for improving the velocity of image processing
并行計算是提高處理速度的有效手段之一，隨著高性能并行處理系統的發展，圖像并行處理技術為提高圖像處理速度提供了更大的空間。 -
Embedded realization includes not only the embedment of special digital signal processing software in universal parallel processing system, but although the embedment of such parallel system in the whole sonar system
本文嘗試了嵌入式實現的方法，不僅包括在通用并行處理系統中嵌入專用的數字信號處理軟體包；而且包括將此并行處理系統嵌入到整個聲納系統中。 -
This parallel processing system can be easily expanded to more complicated architecture to adapt to the various parallel algorithins. in this paper, the main works are as fol1owsf 1. a para1lel signal processing system with four adsp2l060 processors has been developed
本設計開發的并行處理機具有良好的可擴展性，可擴展成具有復雜拓撲結構的信號處理機以適應不同規模的并行演算法的要求。 -
In designing or selecting a topology for a parallel processing system, one fundamental consideration is system - level fault tolerance. in order to improve the fault tolerance, the paper analyses from the two following sides : one is by adding the less links related to the original networks, modifying the topology of the original one, we get higher fault tolerance of the new network ; the other is under the same topology network, ignoring the likelihood of one processor and ail its neighbors failing at the same time, or considering the distribution of the faulty nodes, that is studying the fault tolerance under the conditional connectivity or cluster - fault - lolerance
本文以提高網路的容錯度為目的，從兩個方面分析互連網路的容錯性質：一是在原網路基礎上增加少量連接，使新型網路具有更高的連通度（容錯度為連通度減1 ） ；二是在給定互連網路拓撲結構下，考慮故障處理器發生的概率和故障處理器的分佈狀況，在其中的某一具體條件下，即在條件連通度和簇容錯下分析互連網路的容錯性能，從而得到更高的網路容錯度。 -
Finally discusses several class different multi - dsp extended architecture based on vvp platform. chapter 3 analyzes the significance of dynamic reconfiguration of multi - dsp parallel processing system, introduce run - time reconfiguration technique of fpga. with comparison of the common used dynamic communication network in parallel processor system, proposes the new dynamic reconfigurable multi - dsp system architecture based on run - time reconfigurable fpga
第三章分析了多dsp并行系統體系結構動態可重構的意義，介紹了fpga動態配置技術，比較了現有的一些多處理器動態互連的設計實現方法，在此基礎上，提出了利用局部動態重構fpga技術設計實現實時動態可重構多sharc功能系統的新方法。 -
Artificial neural network ( ann ) is one kind of ai method which is stood up by imitating person ' s brain nerve delivering information. it is one kind of distributed parallel processing system, the acquired results save in the matrix with weight values distributed
人工神經網路是一種模擬人腦腦神經傳遞信息的方式而建立起來的一種人工智慧的方法，它是一種分散式的并行處理系統，其處理結果以權值形式分佈存儲在矩陣中。 -
For the hardware, the device is an advanced data acquisition and parallel processing system required specifically by real - time signal monitoring in power system. a multi - channel sampling and retaining circuit, which makes it possible to acquire and transform data synchronously, is designed. to make the application of the device more flexible, two communication methods are offered, i. e. rs - 232 communication and ethernet communication
硬體設計方面，根據電力系統中數據採集和處理的實際特點，設計了信號的多通道采樣保持電路，實現了多路信號的同步采樣和快速轉換;為了提高裝置應用的靈活性，系統在通訊方式上，除了採用常用的rs - 232通訊方式，還提供了以太網通訊方式。
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