parasitic effect 中文意思是什麼

parasitic effect 解釋
寄生效應
  • parasitic : adj. 1. 寄生的，寄生動[植]物的；寄生體的，寄生質的；（疾病）由寄生蟲引起的。2. 寄食的；奉承的。adv. -cally
  • effect : n 1 結果。2 效能，效果，效力，效應，作用，功效；影響。3 感觸，印象；外觀，現象。4 旨趣，意義。5 ...
  1. Their occurrence trait in winter broad bean field and the inhibiting effect of the parasitic enemies to liriomyza huidobrensis were revealed

    揭示了南美斑潛蠅及其寄生蜂在蠶豆田中的發生規律和寄生蜂對南美斑潛蠅的自然控製作用。
  2. The results indicated that : jaj could selectively stimulate the reprduction of bifidobacteria in vivo and inhibit the growth of e. coli which is a main parasitic basterium in human intestinal tract ; moreover, jaj could apprarently improve intestinal tract function. in tested group, the mice excreted smoothly and the faecal particles of mice were big and wet, but in control group, the faecal particles of mice were small and dry. lt was suggested that inulin may be the important effective component in jaj which promoted the reprduction of bifidobacteria in vivo. at last, the effects of ja on the bile salt resis tance of bifidobacteria were studied. the test proved that : deoxycholic acid na - salt ( dca - na ) had intensely toxical action on blm and bbm ; adding glucose and fructose in media could decrease the lexical action on bbm. but inulin and jap had not apparent effect

    在通過單菌株檢驗和混菌檢驗確立了一種選擇性雙歧桿菌培養基之後，進一步以健康昆明系小鼠為實驗動物，研究了菊芋在動物腸道內對雙歧桿菌的影響，動物實驗結果表明，菊芋汁在體內對雙歧桿菌有選擇性促進生長作用，而腸道中主要條件致病菌?大腸桿菌的生長受到抑制；菊芋中的菊糖成分可能對菊芋在體內選擇性地促進雙歧桿菌生長起了主要作用；此外，菊芋還具有明顯的整腸作用，同對照組相比，飼喂菊芋汁的小鼠排便順利，糞便顆粒大且濕潤。
  3. The dac ' s output voltage can be exported by two groups of line - output structure. the simulation result shows this structure also can low the effect of the parasitic capacitances

    D a轉換器採用了兩組行輸出的電阻串結構，能有效地降低寄生電容對轉換電壓輸出的影響。
  4. In the second part, we introduce the advantages of soi devices together with their corresponding mechanisms : free of latch - up effect, low parasitic capacitance, easy to form shallow junctions and so on

    論文的第二部分介紹了soi器件的優點:無latch - up效應，較低的源漏寄生電容以很容易形成淺結等，並對具體的機理作出了相應的解釋。
  5. The source drain extension ( sde ) structure and its reliability are thoroughly studied. first, it is shown that the sde structure can suppress short channel effect effectively and the parasitic resistance at the sde region has an effect on performance. it is proposed that increasing the dose condition in the sde region can reduce the parasitic resistance and should be adopted to achieve high performance for deep submicron devices

    本文對深亞微米源漏擴展mos器件結構及其可靠性進行了深入研究，首先通過模擬驗證了源漏擴展（ sde ）結構對短溝道效應的抑制， sde區寄生電阻對器件性能的影響以及sde區摻雜濃度的提高對器件性能的改善，指出了器件尺寸進一步減小后，提高源漏擴展區摻雜濃度的必要性。
  6. This paper also presented the structure of soi bjmosfet and discussed and analyzed the advantages of this device by comparing with the bulk bjmosfet. its advantages are as fellow : no latch - up effect, better capability of resisting invalidation, much smaller parasitic capacitance, weaker hot - carrier effect and short - channel effects, and simpler technics, and so on

    通過與體硅bjmosfet比較，討論和分析了soibjmosfet的優點：無閂鎖效應、抗軟失效能力強、寄生電容大大降低、熱載流子效應減弱、減弱了短溝道效應、工藝簡單等。
  7. In this paper, the soi technology is applied to the integrated circuit fabrication. soi technology overcomes some disadvantages of bulk silicon because of its inherent structure. it has the advantages such as no latch - up effect, low parasitic capacitance, high transconductance, simple structure, high density and good anti - radiation

    Soi技術以其獨特的材料結構有效地克服了體硅材料的不足，它具有無閉鎖效應；漏源寄生電容小；較高的跨導和電流驅動能力；器件結構簡單；器件之間距離小；集成度高；抗輻射性能優良等優點。
  8. With the improvement of cmos technology, the density of unit area in ic chips is more and more high. so the power of chips and the internal parasitic effect have been projected

    由於單位面積晶元上mos管的集成度大幅度提高，隨之而來的晶元的功耗以及晶元內部的各種寄生效應的問題就顯得更為突出。
  9. The design flow includes the construction of basic cell libraries, placing & routing, layout verification and post - layout simulation, etc. moreover, the layout design of basic cells and functional modules, the measures of circuit protection and methods to reduce the parasitic effect are also been discussed

    這個流程介紹了與intelm80c287協處理器完全兼容的協處理器的後端設計過程。介紹了協處理器設計過程中基本單元和一些主要功能模塊的設計，以及設計中的保護措施和減少寄生效應的設計方法。
  10. However, some improvements have been made for the distributed rc model, the precision ca n ' t attain the request due to the influence of parasitic effect especially the increasing inductance with the development of interconnect technologies in deep - submicrometer region. so these influences must be taken into consideration and the building of new distributed rlc model for interconnect delay and crosstalk becomes more importance. according to this model, two cases, that is, cmos driving transmission line and interconnect line between chips have been analyzed

    對傳統的分佈rc模型進行了改善，但隨著互連向深亞微米級發展，寄生效應的影響尤其是電感的影響，必須考慮，因此建立新的rlc傳輸模型是很必要的，本文提出了這種新的互連模型，並對cmos驅動互連線和晶元之間互連兩種情況進行了分析，驗證了延時模型是可靠和精確的，並對延時的改善起到了指導作用。
  11. We choose hb qrc convert as the research object. this paper has completely analyzed the circuit work modes, designed an experimental device, analyzed the mam noise source, established the common - mode and different - mode noise current models, extracted the parasitic elements of four pcb layout and simulated each emi level. based on these, it has derived the element which have great effect on pcb emc and has designed the optimized pcb layout

    選擇一種半橋準諧振變換器作為研究對象，對其工作原理進行了詳細的分析，製作了實驗樣機，分析了它的主要干擾源，建立了它的共模、差模噪聲電流等效電路模型，對它的四種不同pcb布局進行了寄生參數提取和電磁兼容模擬，在此基礎上分析得到了影響其電磁噪聲水平的最重要因素，並設計出了最優的pcb布局。
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