parasitic parameter 中文意思是什麼

parasitic parameter 解釋
寄生參數
  • parasitic : adj. 1. 寄生的，寄生動[植]物的；寄生體的，寄生質的；（疾病）由寄生蟲引起的。2. 寄食的；奉承的。adv. -cally
  • parameter : n. 1. 【數學】參數，變數；參詞；參項。2. 【物理學】參量；（結晶體的）標軸。3. 〈廢語〉【天文學】通徑。vt. -ize 使參數化。
  1. Subsequently, we can get the chip s - parameter by adding the negative equipment circuit of the parasitic parameters in the s - parameter model of packaged device

    之後，在有管殼封裝器件的s參數模型中，加上負的寄生參量的等效電路，即可得到管芯的s參數。
  2. The problem in high speed signal process, such as parasitic parameter and gate delay is also the difficulty hi the research

    生成高速，穩定的時鐘信號是本課題的目標。高速信號處理所遇到的常見問題，如寄生參數，門電路延遲是設計難點。
  3. With the software cadence, model establishment and parasitic parameter extraction are made on the main pcb lines of the proposed circuits. equivalent circuit models of common mode combined with differential mode current and noise simulation models are also established on full bridge switching - mode converters. study on the simulation of conducted interference noise is made with the software saber and the effects on the circuits " noise by the main parasitic parameters are also analyzed

    在對全橋開關型變換器電路工作原理分析的基礎上，建立了全橋開關型變換器主要元器件的電磁干擾參數模型，利用cadence軟體對其pcb主要印製導線進行了建模分析和寄生參數的提取，得到了全橋開關型變換器傳導干擾的共模、差模噪聲電流等效電路模型以及噪聲模擬模型，並運用saber軟體進行了傳導性干擾噪聲的模擬研究，分析了主要寄生參數對電路噪聲的影響。
  4. The difficulty in design microstrip pin sp3t switch is the via hole for grounding. we use both the radial parts and the via hole to get a good result. the fin - line pin switch is fully simulated using full - wave analysis, the parasitic parameter and the circuit assemble need to be considered

    微帶結構上過孔微波接地效果的不理想，是微帶單刀三擲開關的難點，本文採用了扇形的微波接地和過孔直流接地結合起來，較好的解決了這一問題。
  5. To make use of parasitic parameter to design the circuit : because parasitic inductance induced by packaging could not only influence the circuit characteristics, but also lead to a design failure, the inductor value needed in the circuit can be designed in the amplifier according to the size of parasitic inductance

    4 、利用寄生參數來設計電路。由於電路的封裝存在寄生電感，其不僅會影響電路的特性，而且可能造成電路設計工作的失敗，所以根據電路所需電感及其值的大小，將之有效的設計在放大器電路中。
  6. The traditional methods of parasitic parameter extraction in eda, which based on the concept of lumped component, have lost their accuracy

    傳統的eda設計中的基於集總電路概念的參數提取演算法已經失去準確性。
  7. Because of the influence of some parasitic parameter in pin diode and circuits, some measure must be taken to compens ate the circuits

    由於pin管和開關電路中存在一些寄生參量的影響，實際製作中可採取相應措施對電路進行補償。
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