rtl gate 中文意思是什麼
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A research is done for studying the reusable design principles of bus function model ( bfm ) and bus monitor for reusability. the functional verification framework is proposed in this dissertation can be apply in soc system level, rtl level and gate level verification. we accumulated experiences to soc functional verification
討論了功能驗證平臺中總線功能模型（ busfunctionmodel ， bfm ）和總線監視器（ busmonitor ）的設計方法，給出了可重用設計的規則；本論文建立的soc功能驗證系統結構，可以應用於較大規模的soc的系統級、寄存器傳輸級和門級的驗證中，通過本課題研究，為國內soc功能驗證積累經驗，為國家超大集成電路的發展奠定一個堅實的基礎。 -
The design of mcs - 51 microcontroller is followed the top - down design way, including system partition coding ( vhdl ) rtl simulation synthesis, gate level simulation ect
對mcs ? 51單片機進行正向設計，包括系統劃分、編寫代碼、 rtl級模擬與綜合、門級模擬等。 -
And the process of functional verification consists of the implementation of rtl ( register transfer level ) simulation, gate level simulation and post - layout simulation in the process of design
驗證最關鍵的是測試方案的制定，而功能驗證的過程是在於在設計過程中實施rtl級模擬、門級模擬和后模擬。
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