sampling clock 中文意思是什麼
sampling clock
解釋
取樣鐘-
The sample and hold circuit is employed by the bottom plate sampling technique, which could not only cancel the charge injection error but also eliminate the effect of clock feed - through
采樣保持電路設計採用了電容下極板采樣技術，不僅有效地避免了電荷注入效應引起的采樣信號失真，而且消除了時鐘饋通效應的不良影響。 -
Of course the sampling clock is itself a digital signal
時鐘本身也是數字信號，也會干擾模擬電路。 -
The paper first reviews the research background and actuality of the filter " s design in china and other country, introduces the meaning of the project and the work of the paper, narrates the theory of the switched - capacitor network and the basic switch building blocks, analyses the related factors of the design of sc filter. such as the selection of the architecture, the trade off of the opamp " s gain, bandwidth, phase margin, slew rate and setting time, the effect of the switch " s on resistor, how to reduce the charge injection and the clock feed - through, the power consumption and the selection of the sampling frequency and so on
本文首先回顧了濾波器設計的國內外研究背景和現狀，介紹了本課題提出的意義以及本文的主要工作，論述了開關電容網路原理和基本開關模塊，分析了開關電容濾波器設計的相關因素：電路結構的選擇，對運算放大器設計中高增益、寬帶寬、相位裕度、轉換斜率和建立時間等的折中考慮，開關的打開電阻對電路的影響，開關電容電路中怎樣減少電荷注入和時鐘饋通，以及整個電路的功耗問題和采樣頻率的選擇等。 -
And a kind of 16 - step automatic selective programmable amplifying circuit is designed in volume resistivity measuring circuit, so as to handle sampling little and broad signal. the control and disposal system with the core of microchip at89c55wd is analyzed on chapter 4. main function unit such as the interface circuit of lcd display and keyboard, the interface circuit of micro - printer, real time clock ds12c887, and hardware anti - jamming technique are discussed
本文還設計了以at89c55wd單片機為核心的控制處理系統的外圍介面電路及其軟體，對主要功能部分進行了分析，主要包括：鍵盤液晶顯示介面及界面設計、微型印表機介面、實時日歷時鐘晶元ds12c887 、單片機與單片機及單片機與上位機的通信設計以及控制系統硬體抗干擾措施等。 -
The article also includes the work as follows : 1. finished designing the hardware collective circuit and its controlling program, and using the dissynchronous fifo technique and independent clock circuit to solve the problem of high - accuracy regular - frequency sampling and the match system speed
論文還完成了以下工作： 1設計現場診斷儀的硬體採集電路及相應控製程序。應用異步fifo技術和獨立時鐘電路，解決了高精度定頻率采樣以及系統速度匹配問題。 -
The fpga of xilinx inc. works as a important part, with which many functional modules, including a controller of lcd display, a fifo ( first in first out ) memory, a controller of sampling clock, and so on, were implemented
Xilinx公司的fpga （現場可編程門陣列）作為系統的外圍控制器，實現系統的其他很多功能模塊，包括lcd （液晶顯示）控制器、測頻和測周模塊、 fifo （先進現出存儲器） 、采樣時鐘控制器，等等。 -
In the time - domain, based on the principle of random sampling of dso. two way ( " time amplifing in dual slope integral " and " time - voltage convert " ) are implemented to measure the time between the system triger and writing clock. thus random sampling interpolate can be done to measure repeated signal in high frequency with the a / d convert and controller which frequency are lower
在時域，根據數字示波器隨機取樣原理，用兩種方法（雙斜率積分時間放大測量方法和時間? ?電壓轉換測量方法）測量數字示波器系統觸發和采樣寫時鐘間時間間隔，用低速a / d轉換器及控制器進行模?數轉換和控制，以此進行隨機取樣內插，從而實現了對高頻率重復信號的測量。 -
The sampling clock generator must also have adequate spectral purity
時鐘發生電路固有的抖動應該足夠小。 -
Figure 5. 36 shows the relationship between sampling clock jitter and snr previously presented
圖5 . 36顯示了采樣時鐘抖動和信噪比之間的關系。 -
To achieve this the sampling clock should be isolated as much as possible from the noise present in the digital parts of the system
為此，時鐘信號應該盡可能地與電路中強噪聲的部分隔離開，例如數字電路。 -
The adc aperture jitter must be minimal, and the sampling clock generated from a low phase - noise quartz crystal oscillator
Adc的孔徑抖動必需盡可能的小，而且要使用低相位噪聲的石英晶體振蕩器作為采樣時鐘發生器。 -
The ep2s15 of altera company, work as the system ’ s peripheral controller include fifo ( first in first out ) memory and sampling clock controller
Altera公司的ep2s15作為系統的外圍控制器，實現對系統的fifo （先進先出存儲器）與采樣時鐘的控制。 -
As to phased array receiving, a scheme of separating the delay clock and sampling clock is explicated, which effectively enhance the phased receiving delay resolution
對于相控接收延時，本文闡述了一種將延時時鐘和采樣時鐘分離的方案，有效地提高了接收延時解析度。 -
Based on the coherent reception theory of radio signals and the theory of digital signal processing, the effects of carrier frequency offset, sampling clock offset, and symbol timing offset on ofdm signals are exploited. a series of amendments and new algorithms is derived from the in being algorithms of guard interval based symbol timing and frequency offset estimation, frequency - domain frequency offset, sampling offset, and symbol timing offset estimation
以無線信號的相干接收和數字信號處理理論為基礎，就載波頻偏、采樣鐘偏差和符號定時偏差對ofdm信號的影響進行了分析，對基於保護間隔的符號定時與載波頻偏估計演算法和多種現有頻偏、采樣鐘與符號定時偏差的頻域估計演算法進行了研究，提出了一系列改進措施與新演算法。 -
Software design includes many aspects, such as design of interface, interrupt and clock control, monitoring, etc. sampling and accessing quickly data of chromatogram peak is an important tache to ensure analytic and real time performance of chromatograph, fifo make high - speed input and output of a / d sampling data possible, and expended memory, instead of disk, save a great deal of peak data and process parameter
硬體系統由cpu 、 a / d 、 d / a 、顯示驅動、實時鐘五個模塊組成，軟體設計包括譜峰數據的高速採集和存取、人機界面的設計、中斷和實時鐘控制、監測控制等方面的工作。譜峰數據的高速採集和快速存取是保證工業色譜儀分析性能和實時性的重要環節，採用了fifo存儲器技術實現a / d采樣數據的高速輸入輸出，使用擴展內存代替硬盤存貯過程參數和海量的譜峰數據。 -
Especially it allows various types of interruptions of external digital input, timer output and a / d conversion, each type of interruption has its own role in the signal measurement or in exact pace control, its fifo buffer function makes it possible to work at the sampling rate of 200k samples per second without carrying over - burden interruption rate, its latch type external interrupt request along with its high frequency clock makes a precise locating of pulse edges possible
該控制系統在工作過程中，有多種產生於不同部件的信號需要檢測，其中有模擬輸入信號十三路，數字輸入信號三路，通過數據採集和信號分析，判斷該控制系統工作是否正常。結合系統檢測的具體要求，本論文從硬體設計和軟體設計兩個方面，實現了數據採集系統的硬體介面電路和軟體演算法。 -
The effects of sampling clock jitter on signal - to - noise ratio ( snr ) and effective bit ( enob ) performance discussed in section 3 are even more dramatic in undersampling applications because of the higher input signal frequencies
在第三章討論的采樣時鐘抖動對信噪比和有效位性能的影響在欠采樣應用中因為更高的輸入信號頻率顯得更有戲劇性。 -
2. the microcomputer - based greenhouse monitoring & controlling system has been developed around an atmel microcontroller which is reinforce by multiplex a / d sampling module ; large volume data on - line storage module ; real - time clock module ; keyboard & display man - machine interaction module ; system monitoring module and communication interface module and so on
溫室微機測控系統的設計以美國atmel公司的微控制器為核心，擴展了多路a d採集子模塊、大容量數據在線存儲子模塊、實時時鐘子模塊、鍵盤顯示人機對話子模塊、系統監視子模塊、現場總線系統和上下位計算機通訊子模塊等等。 -
The difference clock delay match technology adjusts the two channel ad analog clock phase and implements the two way ad uniformly - space sampling
差分時鐘延遲匹配技術通過對兩路ad的采樣時鐘進行相位調整，實現了兩路ad的等間隔采樣。 -
The relationship between the clock jitter and the sampling sequence of a sine wave is studied, and a new method to measure the jitter and distribution of a clock signal with pico - second resolution is proposed using adc sampling based on estimating method of the parameters in sine signal
摘要研究了時鐘抖動與正弦信號的采樣序列之間的關系，並在正弦信號參數估計法的基礎上，提出一種利用adc采樣測量皮秒量級的時鐘抖動大小和分佈的新方法。
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