serial-parallel register 中文意思是什麼
serial-parallel register
解釋
串并行寄存器-
The third row of the table represents synchronous parallel loading of the register and states that if s1 and s0 are both high, then, without regard to the serial input, the data entered at a is at output qa, data entered at b is at qb, and so forth, following a low - to - high clock transition
表2中第三行表示計數器的同步平行的加載，和表明如果s1和s0為高電平，那麼它就不是連續輸入，在時鐘由低向高跳變后，在a端的數據輸入則在qa端輸出，在b端的數據輸入將在qb端輸出，等等。 -
The serial a / d transformation and the channel isolation technology are adopted. eight - channel parallel data acquisition and test data time - sharing storage are realized. verilog hdl ( hardware description language ) is adopted to design the vxi register - based interface circuit and control circuit of each channel
以fpga （ fieldprogrammablegatearray ）為控制核心，採用串列a / d變換器和通道隔離技術，實現了8通道并行採集和測試數據分時存儲功能，利用veriloghdl （ hardwaredescriptionlanguage ）設計vxi寄存器基介面電路及各通道的控制電路。
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