shared processor 中文意思是什麼
shared processor
解釋
共享處理機-
As the requirements of its function, a bus control interface board has already been designed. also the paper have provided the scenarios demonstration for the bus control interface board ( bcib ), the design for the protocol of communication, the hardware for bcib, the software for bcib, and the software for the processor ' s communication. while the analysis for the capability of real - time and the calibration and test for subsystem have been also finished. during the design, the system advanced ability, reliability, resources availability and the cost - efficency ratio are considered. the issus such as system integrated control, mutual exclusion of the shared storages, generation of handshaking signal and system self - test were resolved
本論文主要對航空自衛系統的綜合化方式進行了深入研究，並按其功能等方面要求，對航空自衛系統綜合化總線通信模塊進行了設計，主要完成了總線通信模塊方案論證、通訊協議設計、總線通信模塊硬體設計、總線通信模塊（ bcib ）軟體設計、處理機通信軟體設計、實時性分析、系統調試、試驗等項工作，在設計過程中，綜合考慮了系統先進性、資源利用率、費效比及可靠性等因素；重點解決了系統綜合控制方式、共享存儲器互斥、握手信號產生及系統自檢測等問題。 -
Smpdca architecture has six outstanding excellences : complexity of the control logics of smpdca is lower than large scale superscalar ; supplying shortest inter - processor communication latency using the shared li data cache ; no cost to maintain cache coherence ; hit rate of data cache increase ; easy to reuse many softwares of symmetric multiprocessor ( smp ) ; exploit the parallelism of applications from many levels. this paper present the architecture model of smpdca, and illustrated its function units, and discussed its key techniques, and analyzed the address image policy of multi - ported cache
Smpdca結構具有六個突出優勢：相對于大規模的超標量結構而言， smpdca結構的控制邏輯復雜性明顯要低得多；相對于通過共享主存來實現處理器之間的通信的結構而言，通過一個共享的第一級數據cache來實現處理器之間的通信的smpdca結構能夠提供非常小的處理器之間的通信延遲；沒有cache一致性維護開銷；數據cache命中率提高；便於smp （對稱多處理器結構）的軟體重用；從多個層次上開發程序的并行性。 -
A bus shared heterogeneous architecture consisting of one or more instruction set processor cores, one or more dedicated hardware ip cores and one or more on - chip memories usually provides a good solution
基於總線互連的由一個或多個指令集處理器核、一個或多個專用硬體ip核、一片或多片片上存儲器構成的異質體系結構成為媒體系統晶元的合理選擇。 -
In particular, nearly every modern processor has instructions for updating shared variables in a way that can either detect or prevent concurrent access from other processors
特別是，幾乎每個現代處理器都有通過可以檢測或阻止其他處理器的並發訪問的方式來更新共享變量的指令。 -
If the machine does not support the shared processor capabilities, the
如果機器不支持共享處理器能力， -
To use the shared processor pool
以使用共享的處理器池。 -
In case the machine doesn t support the shared processor capabilities, the
在機器不支持共享處理器能力的情況下，應該將 -
This example shows how to count licenses when exploiting the virtualization capabilities available on the ibm eserver p5 and ibm eserver i5 systems that allow you to create shared processor pools
這個例子展示在利用允許創建共享處理器池的ibm eserver p5和ibm eserver i5系統上可用的虛擬化能力時，如何計算許可數。
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