signal delay 中文意思是什麼
signal delay
解釋
訊號延遲-
By changing of the difference of write address and read address, a delayed signal from read port is achieved. the two methods have different idea but reach the same goal and have the properties that are pure digital delay, little error, compendious circuit and maneuverability
兩種方法異曲同工，為純數字延遲，具有抗干擾性強、誤差小、電路簡明，可操作性強等優點，既體現了設計的多樣性，又體現了fpga設計的靈活可編程特性。 -
In all kinds of complicated network, oriented linking and unlinking, communication frequency resource is strained, and bandwith to transmitting audio frequency signal is too restricted, complicated and fluky, while audio frequency data exponential have been increased in the last several years. under the circumstances, based on the research of predecessor, this paper studies wavelet analysis ' s maths gist and practices significance on signal process, and puts forward a optimized wavelet package condensation arithmetic to process audio frequency data, which gives attention to coding efficiency, multirate and compression delay. simulation experiment on the arithmetic has been done by matlab
針對無連接和面向連接的各種復雜網路環境下，通信頻帶資源緊張，音頻傳輸帶寬有限且復雜多變，而各種音頻數據又日益增多的局面，本文研究小波分析在信號處理方面的數學依據和在數據壓縮方面的實際意義，在前人不斷工作的基礎上，提出了一種優化小波包變換編碼方案用於音頻數據的壓縮演算法，兼考慮了編碼效率、多碼率和壓縮時延多個方面，並在matlab環境下做了模擬實驗，對各種音頻信號及多種小波函數做了模擬結果比較，實驗結果證明該演算法可以在一定計算復雜度下可以很好地改進壓縮效果，達到多碼率下實現實時編解碼的過程，在高速dsp晶元等硬體設備支持下，可以有效應用於實際復雜多變信源編碼。 -
Delay line oscillator is composed of broadband amprifer adjustable attenuator and saw sensor device. after output signal of delay line oscillator is smoothed, it mixes with 109mhz local oscillation signal. its differential frequency signal is smoothed by low - pass filter trimmed by shaping circuit and processed by digital processing circuit
延遲線振蕩器由寬帶放大器、可調衰減器和聲表面波質量傳感器件構成。延遲線振蕩器輸出信號經濾波后與109mhz的本機晶體振蕩器輸出信號相混頻，通過低通濾波取其差頻，並經整形後由數字信號處理電路處理。 -
7. in chapter 8, a new method for estimating the doppler and multipath time delay of the overlapping echoes for lfm pulse radar by only one period pulse signal is presented
7 .在第八章提出了一種對lfm脈沖雷達回波d叩pler頻移和多徑時延進行聯合估計的方法。 -
Chapter 4 designs and determines the parameters of the algorithm adopted in the instrument system. analyzes and compares the different effects to frequency estimation when using digital filters with different group delay ; determines the data length, a parameter of frequency estimation ; introduces the method of available judgment of sensing signal and determines the judgment threshold as well
第四章設計和確定了儀器系統軟體演算法的部分參數：分析和比較了不同群延遲特性的數字濾波器對頻率估計的影響；確定了影響頻率估計參數?數據長度的取值規律；給出了判斷傳感信號有效性的檢測方法並確定了檢測門限的取值規律。 -
This paper proposes a handoff algorithm using dual - window measurements in cellular mobile communication system. the proposed algorithm can provide a suitable balance of probability and delay of handoff. an analysis model of this algorithm is given in this paper. the proposed algorithm is especially fitted to the situation which mobile station needs to measure the signal strength from many base stations
本文提出了一種新的蜂窩移動通信系統越區切換測量演算法，該演算法採用了兩個長度不同的測量窗口，有利於在切換時延和切換平均次數這對矛盾之間取得更為有效的平衡，特別適用於需要對多個基站進行切換測量的情況.同時本文給出了基於矩形窗口的雙窗口切換測量演算法數學分析模型，及數值分析結果 -
To increase the bearing accuracy of amplitude - comparison, the multi - channel system was chosen, the angle of reaching of moving antenna pattern serial was estimated from the frequency domain using the phase - delay estimating method, and at the same time, the selection of antenna, quantization of signal and touch switches were optimized in concrete engineering practice, and so the requirement of the index was satisfied
為提高比幅測向的精度，選用多通道體制，採取相位延時估計法從頻域來估算移動天線方向圖系列的達到角，同時在具體的工程實現上對天線選取、信號的量化、去摸開關等進行優化，從而滿足指標要求。 -
The clock recovery block of usb2. 0 transceiver macrocell consists of phase locked circuit, such as pll and dll ( delay locked loop ). this block use external crystal 12mhz sin signal to produce 60mhz, 120mhz, 480mhz clock signal, and can recover colock signal form date wave. it can support 480mbps ( hs ) and 12mbps ( fs ) word speeds as defined in usb2. 0 specification.
目的是用鎖相環電路? pll和dll （延遲鎖相環）實現usb2 . 0收發器宏單元utm的時鐘恢復模塊。其中pll環路構成的時鐘發生器將外部晶振的12mhz正弦信號生成60mhz 、 120mhz 、 480mhz等本地時鐘信號。 dll環路依據本地時鐘信號對外部數據信號進行時鐘恢復。 -
In the digital inverter, we adopt the technology of digital dynamic waveform correction, which can compensate the delay between control signal and output waveform, and ensure the accuracy of control. at the same time, the technology of digital dc component adjustment was introduced, by which we can exactly compensate the control signal, and realize adjusting dc component of output on the premise of output performance
在基於dsp的數字變換器平臺中，採用全數字波形校正技術，完全補償了控制信號延時、功率管開關延時以及死區時間對輸出spwm波形所產生的畸變，充分保障了變換器控制的準確性；採用數字直流分量調節技術，可以精確地對控制信號進行補償，在充分保證輸出性能的前提下，實現了輸出直流分量的調節。 -
For high stability of the system, with the realization of hardware of the system, the second part of this paper starts from the transmission line theory, and studies the signal integrity problem of high - speed circuit system in light current. the causes of these signal integrity problems, such as signal delay, reflection, crosstalk, ground bounce noises and etc. are analyzed in theory. combined with actual design, key points of design and standard design flow of general high - speed, high - precision printed circuit board are summarized, which has been applied in actual system, and good effect has been achieved
為使系統具有較高的穩定性，本文第二部分結合該處理器的硬體實現，從傳輸線理論出發，研究了弱電情況下高速電路印刷電路板中的信號完整性問題；從理論上分析了延遲、反射、串擾以及地彈噪聲等信號完整性問題產生的原因；結合實際設計，總結了一般高速、高精度印刷電路板的設計要點和標準設計流程，並在實際系統中獲得了應用，取得了很好的效果。 -
The influence of the multi - layer cabling structure in integrated circuit on the signal delay
大規模集成電路多層布線結構對信號延時的影響 -
This logic is designed containing input signal delay, event type classification, event pre - scaling and timing logic and works in pipeline mode under control of 20mhz clock which ensures no dead time contribution
主觸發邏輯在20m時鐘下以流水線的方式工作，保證沒有死時間的產生。第二個例子是任意數字信號發生器的設計。 -
Wirings of the poly layer are always utilized under the silicon grid technics. to control the macro - cell signal delay and improve signal integrality, the crossing among different nets must be averagely distributed to reduce the number of layer permutation. the metal layer wirings should be maximized and the length of poly layer wiring in each net should be minimized
硅柵工藝晶體管級布線利用多晶層走線，為了控制宏單元時延性能及改善信號完整性形態，關鍵是不同線網間交叉的均衡分配以減少走線的換層次數，最大化金屬層走線以及每一線網多晶層走線長度的有效控制。 -
The drawbacks of the former one are that higher power is required to reach a satellite at that distance and a substantial round trip signal delay is inevitable
前者的缺點是由於距離較遠因而要求較大的信號功率以及存在較長的信號延遲，而後者則由於衛星數目巨大而費用昂貴。 -
By analysis, we have found that the output of if dsss / bpsk signal delay and multiplication processing is composed of
該法處理輸出的頻譜包含寬帶成分導致其載頻估計能力較差。 -
The research object of traditional dm method is the output of base - band dsss / bpsk signal delay and multiplication processing or the base - band component of output of if dsss / bpsk signal delay and multiplication processing
傳統的延遲相乘法研究對象是基帶信號的延遲相乘輸出，或中頻信號延遲相乘輸出的基帶部分。 -
Effect of atmosphere on satellite navigation signal delay and correction method
大氣層對衛星導航信號的時延影響及修正 -
( 4 ) the signal delay commission is done well by the controller
（ 4 ）所設計的信號延時系統能夠穩定、準確的完成信號延時工作。 -
Absolute signal delay
絕對信號延時 -
The hardware system is consisted of ccd camera, video capture card, pcl - 731a digital input / output card, signal delay controller, industry computer and outside executing set
系統硬體部分由ccd彩色攝像頭、圖像採集卡、 pcl - 731a數字量i o卡、信號延時器、工業用計算機和外部執行機構組成。
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