stage circuit 中文意思是什麼
stage circuit
解釋
分級電路-
Based on the current signal from the proceeding stage, the first order - modulator designed could be simplified in the precondition of performance satisfaction, and it is good in accomplishing signal conversion and could be incorporated with the forestage bandgap circuit
根據前級溫度傳感電路的電流信號，在滿足性能要求的前提下盡量簡化電路，設計出的一階-調制電路不但很好地完成了信號轉換，而且更符合一體化結構的要求。 -
A complementary input stage, which consists of a p - channel pair and a n - channel pair, was used in the circuit, so that the common mode input range can extend from rail to rail. a dcls is used to shift the n - transistor curve leftward to overlap the p - transistor curve properly and keep constant transconductance in the whole common mode input range
輸入級採用pmos差分輸入對和nmos輸入差分對並聯的結構，從而實現共模輸入范圍擴大到電源的正負兩端，並且通過兩個源級跟隨器平移nmos輸入管跨導曲線，使nmos輸入管和pmos輸入管跨導曲線的適當交疊，從而保持了這個輸入級的跨導在整個共模輸入范圍內保持恆定。 -
The three - order modulator has a 2 - 1 cascaded structure and 1 - bit quantizer at the end of each stage, the modulator is implemented with fully differential switched - capacitor circuits. and then, the discussion will begin by exploring the design of various circuit blocks in the modulator in more detail, i. e., ota, switched - capacitor integrator, quantizer, two - phase non - overlapping clock signal, etc., at the same time, these circuits will be simulated in spectre and hspice. at last, the whole cascaded modulator will do behavioral level simulation by matlab soft and simulink toolbox
本論文中，首先介紹模數轉換器的各種參數的意義，以及一階sigma - delta調制器和高階sigma - delta調制器的原理;給出解決高階單環sigma - delta調制器不穩定性的方案，引入級聯結構調制器，特別針對級聯結構調制器中的失配和開關電容積分器的非理想特性進行詳細的討論;本設計的sigma - delta調制器採用2 - 1級聯結構和一位量化器，調制器採用全差分開關電容電路實現;同時對整個調制器的各個模塊進行了電路設計，包括跨導放大器、開關電容積分器、量化器、兩相非交疊時鐘等，並利用hspice和spectre模擬工具對這些電路進行模擬測試;最後，利用matlab軟體和simulink工具對整個級聯調制器進行行為級模擬。 -
Abstract : a new clock - driven eco placement algorithm is presented for standard - cell layout design based on the table - lookup delay model. it considers useful clock skew information in the placement stage. it also modifies the positions of cells locally to make better preparation for the clock routing. experimental results show that with little influence to other circuit performance, the algorithm can improve permissible skew range distribution evidently
文摘:提出了一種新的時鐘性能驅動的增量式布局演算法，它針對目前工業界較為流行的標準單元布局，應用查找表模型來計算延遲.由於在布局階段較早地考慮到時鐘信息，可以通過調整單元位置，更有利於后續的有用偏差時鐘布線和偏差優化問題.來自於工業界的測試用例結果表明，該演算法可以有效地改善合理偏差范圍的分佈，而對電路的其它性能影響很小 -
Secondly, compared with some other kinds of comparator structure and based on the preamplifier - latch fast - compare theory, a novel topology of cmos preamplifier latch comparator circuit is presented. considering trade - off between kickback noise and power dissipation, reference resistance value is optimized. according to the encode demands of different stage resolution, clock - control encode circuit is designed
其後，在具體的子adc設計中，對比各比較器類型的優缺點，並基於預放大鎖存快速比較理論，提出一種新型高速低功耗預放大鎖存比較器電路拓撲;根據adc系統所允許的參考電壓最大波動限制，在回饋噪聲對輸入參考電平的影響和功耗之間折衷，確定優化的參考電阻串阻值;根據不同級精度的編碼要求，設計出時鐘控制編碼電路。 -
After which, the battery will be charged by large constant current to allow the fast charging. finally, the constant voltage charging is adopted to guarantee the battery was charged to its full capacity. under the condition that the temperature has raised to a certain threshold at the constant current charging stage, the over temperature circuit is performing and it provides a compensation current which switches the system to constant temperature charging mode with the intention of protecting the ic
即在充電初期採用較小的電流對電池進行預處理，對出現過放電的電池進行修復和保護;然後採用較大的恆定電流對電池充電，實現快速充電的目的;最後採用恆定壓充電，確保電池充滿;在恆流充電階段，當晶元溫度上升到一定程度時，晶元過熱保護電路開始工作，該電路以提供充電補償電流的形式使充電進入恆溫充電模式，對晶元進行保護。 -
( 3 ) modeling of the asymmetrical half bridge converter in the thesis, a small average circuit model of asymmetrical half bridge converter power stage is established by method of state space averaging. in term of it, a system model of total converter is founded. the characteristic of stabilization and dynamic is analysed and the compensator is designed basing of it
（ 3 ）不對稱半橋dc dc變換器的建模分析採用狀態空間平均法建立了不對稱半橋變換器功率級的小信號平均電路模型，在此基礎上建立整個變換器系統模型，對系統的動態特性和穩定性進行了分析並設計了補償器。 -
Thirdly, the relative theories of the limiter and rectifier are studied. in order to make the passive responder work stably under the conditions of large dynamic range of the receiving power and the high efficiency requirement, a two - stage limiter circuit and a voltage - doubler rectifier circuit with several diodes parallel are developed
3 ，對應答器地面裝置中的能量轉換電路進行了研究，針對應答器地面裝置接收到的載波功率具有大動態范圍的特點以及系統能量轉換的高效率要求，設計了一種兩級級聯二極體限幅電路和多管並聯的倍壓整流電路。 -
Describes the design and realization of partial run - time reconfigurable fpga in detail. in order to reduce the affect of the reconfiguration time on system execution time, mostly static circuit design method in logical design stage and incremental routing method in component implementation stage are proposed. the fft parallel processing algorithm is examined through vvp platform
本章詳細闡述了基於vvp平臺的多sharc功能插板的具體硬體實現，以動態重構fpga設計為核心，論述了局部動態重構fpga設計流程和方法，提出了極大靜態電路邏輯設計方法和遞增式布線方法，以達到減小動態重配置時間，提高系統運行效率的目的。 -
Secondly, the encoder circuit of quasi - cyclic which can realize low encoding complexity are designed and implemented. three encoder circuit are designed respectively with feed shift - registers and logic gates : sraa - based serial qc - ldpc encoder ; sraa - based parallel qc - ldpc encoder ; two - stage qc - ldpc encoder
採用反饋移位寄存器與邏輯門設計了三個典型的編碼器電路:基於sraa電路的串列準循環ldpc碼編碼器;基於sraa電路的并行準循環ldpc碼編碼器;二階編碼電路。 -
A novel high - power pollution - free smps is presented in this paper, which accomplishes simultaneously the goal of soft - switching pwm, the input / output isolation, the output voltage regulation and three - phase pfc with a single - stage power processor and simple pseudo - phase - shift control circuit. therefore, compared with the normal two - stage system, the single - stage power supply has simpler structure, lower cost, higher efficiency and easier to control. the proposed smps can be used in the three - phase power system, and can output high power over kw - order and input / output ( i / o ) isolation dc power supply
本文提出的新型無污染大功率開關電源正是採用三相三線制輸入電源，利用單級偽相移零電壓零電流開關脈寬調制（ pps - zvzcs - pwm ）全橋變換器完，成功率因數校正（ pfc ）和輸出電壓快速調節、隔離的雙重功能，並且該變換器開關管在零電壓或零電流下通斷，顯著的減小了emi 。 -
Since the early 1990s, when the electronics industry came to the stage of digital technology, china has broken through in high - end series personal computers and servers, large - scale parallel computer systems, chinese electronic publishing systems, large - scale spc exchanges for central offices, mobile communications systems, sdh wdm fiber communications systems, thin route satellite communications systems, new generation digital video terminals, manufacturing technology for 0. 8 - 0. 35 m cmos integrated circuit chips, etc
到90年代進入數字技術階段，高檔系列微機和服務器產品、大規模并行計算機系統、中文電子出版系統、大型局用數字程式控制交換機、移動通信系統、 sdh波分復用光纖通信系統、稀路由衛星通信系統、新一代數字視頻終端、 08 ? 035微米cmos集成電路晶元製造技術等，都有突破性進展。 -
At the same time, essential protective electro circuit is designed for safe. it chooses pc bus industry programmable computer and programmable controller as the host computer and designs two independent systems to control hoist or lower the stage and orchestra separately. for the sake of running safely, it applies ac motor with brake as the power device that adopt frequency conversion mode and inter lock and journey switch in electric circuit
設計中選擇了pc總線工業控制機和可編程序控制器作為控制系統的主機，設計了兩個獨立的系統分別控制升降舞臺和升降樂池，採用了制動電機作為舞臺升降的拖動裝置，電機的調速方法選擇了可以無級平滑調速、經濟節能的變頻調速方法，並在電氣上採用互鎖和行程開關來保證舞臺機械設備的安全運行。 -
The gain stage operates at a constant level regardless of the setting of the master level control, and so the sound of this circuit will not alter at various level settings
無論主音量控制的位置如何，放大級都可以工作於一個穩定的電平，並且不同的音量設定不會引致該電路的音色變化。 -
The principle of operation, the selection of snubber circuit, the design of the coupling inductor and the relationship between the dc / dc and dc / ac converters are illustrated and verified on a 1kw experimental circuit. a two - stage dc / dc converter consists of a boost and ppfc is presented in this paper through further research
文章詳細分析了電路工作過程，給出了緩沖電路的選取原則及耦合電感的設計，討論了該ppfc與后級dc / ac逆變器連接工作時的相互影響，並通過模擬分析和一臺1000w實驗樣機進行了原理驗證。 -
Second, we simulate and optimize the circuit and debug the first stage, the drive stage power amplifier
然後在ads中對設計電路進行了模擬優化，對前級、驅動級功率放大器進行調試。 -
As for the choice of the circuit ' s topology, the pfc stage is adopted boost structure and the pwm stage is adopted two transistors forward after several sorts of advantages and deficiencies of circuit ' s topology are compared
在電路拓撲的選擇上，比較了各種電路拓撲的優缺點，最後選定前級pfc電路採用boost結構，后級採用雙管正激電路。 -
A push - pull output stage was used in the circuit to extend output voltage from rail to rail and a class ab biasing is used to improve the power efficiency of the circuit
輸出級採用共源結構的互補推挽輸出結構，提高了輸出電壓的動態范圍。並使用甲乙類的輸出結構，提高了電路的功率效率。 -
The proposed approach enables parallel execution of conventional lza and its error detection, so that the error - indication signal can be generated earlier in the stage of normalization, thus reducing the critical path and improving overall performance. the circuit implementation of this algorithm also shows its advantages of area and power compared with other previous work
本文提出了一種新型的基於錯誤糾正機制的前導0預測演算法，該演算法在傳統非精確演算法的基礎上增加了對其結果出錯時的預判機制和規格化過程中的實時糾正機制，從而實現了尾數和規格化時的精確移位，降低了浮點加減運算的關鍵路徑延遲。 -
In order to keep away from the unstable area and maintenance the system stability in wide output range, how to design the two - stage circuit parameters is a question for discussion
如何設計前後級的電路參數，保證寬范圍輸出電壓條件下系統的穩定工作?本文對此問題進行了研究分析。
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