standard cell 中文意思是什麼

standard cell 解釋
標準單元
  • standard : n 1 標準，水準，規格，模範。2 旗；軍旗，隊旗；【徽章】標幟，標記；旗標，象徵。3 【植物；植物學】...
  • cell : n 1 小室，單室；隔間，艙；〈詩〉茅舍；（單個的）蜂窩，蜂房。2 〈詩〉墓穴，墓。3 （大修道院附屬的...
  1. Abstract : a cad tool based on a group of efficient algorithms to verify, design, and optimize power / ground networks for standard cell model is presented. nonlinear programming techniques, branch and bound algorithms and incomplete cholesky decomposition conjugate gradient method ( iccg ) are the three main parts of our work. users can choose nonlinear programming method or branch and bound algorithm to satisfy their different requirements of precision and speed. the experimental results prove that the algorithms can run very fast with lower wiring resources consumption. as a result, the cad tool based on these algorithms is able to cope with large - scale circuits

    文摘:介紹了一個基於標準單元布圖模式的電源線/地線網路的輔助設計集成工具.它應用了一系列高效的演算法，為用戶提供了電源線/地線網路的設計、優化和驗證的功能.非線性優化技術、分枝定界演算法和不完全喬萊斯基分解的預優共軛梯度法是該工作的三個主體部分.用戶可以選擇使用非線性規劃的方法或者幾種分枝定界方法來滿足他們對于精度和速度方面的不同需求.實驗結果表明，文中所提供的演算法可以在很快的運行速度下實現更低的布線資源佔用.因此，在這些有效演算法基礎上實現的輔助設計工具具有處理大規模電路的能力
  2. Abstract : a new clock - driven eco placement algorithm is presented for standard - cell layout design based on the table - lookup delay model. it considers useful clock skew information in the placement stage. it also modifies the positions of cells locally to make better preparation for the clock routing. experimental results show that with little influence to other circuit performance, the algorithm can improve permissible skew range distribution evidently

    文摘:提出了一種新的時鐘性能驅動的增量式布局演算法，它針對目前工業界較為流行的標準單元布局，應用查找表模型來計算延遲.由於在布局階段較早地考慮到時鐘信息，可以通過調整單元位置，更有利於后續的有用偏差時鐘布線和偏差優化問題.來自於工業界的測試用例結果表明，該演算法可以有效地改善合理偏差范圍的分佈，而對電路的其它性能影響很小
  3. Based on generation and processing of phase conflict graph, a new method is presented to fully and accurately verify the phase compatibility of dark - field standard cell layouts, which are produced according to conventional design rules

    摘要介紹了一套基於相位沖突圖的生成和處理的新方法，可以準確、全面地對由傳統方法設計的標準單元版圖（暗場）進行檢查。
  4. The second is about verification of alternating psm manufacturability and this part introduces a new method based on standard cells to resolve the phase conflicts, including for dark field and for clear field. the method has the capabilities of verifying standard cell layout, locating features with phase conflicts and giving out suggestion for modification

    第二部分針對由傳統方法設計出的版圖不能滿足交替移相掩模要求的問題，介紹了一種基於標準單元的交替移相掩模可製造性驗證與設計的演算法，包括針對暗場和亮場兩種不同環境版圖的演算法。
  5. 5 hong x l, jing t, xu j y, bao h y, gu j. cnb : a critical - network - based timing optimization method for standard cell global routing

    即：每隻螞蟻各自維護一個訪問結點列表，記錄已經訪問過的結點，以此避免重復訪問同一個結點。
  6. Measurement of emf of each additional standard cell, in the same enclosure

    測量置於同一控溫箱內每一額外標準電池的電動勢。
  7. A phase - compatibility rule checker for standard cell layout designed with alternating psm

    一種用於標準單元版圖交替移相掩模相位兼容性規則檢查的工具
  8. A soft - ware implementing this method is presented as well, which has the capabilities of verifying standard cell layout, locating features with phase conflicts and giving out suggestions for modification

    基於此方法的軟體工具能夠檢查標準單元版圖，找出不符合交替移相掩模設計要求的圖形，並給出相關的修改建議。
  9. Abstract : a new algorithm w - ecop is presented to effect incremental changes on a standard cell layout automatically. this algorithm deals with cell inserting and cell moving based on rows instead of on cells as most placement algorithms usually do. an integer programming problem is formulated to minimize the adjustment on the initial placement and a heuristic method is presented to search for a shifting path so as to optimize the wirelength. test of w - ecop on a group of practical test cases shows that the algorithm can successfully accomplish incremental placement with good quality and high speed

    文摘:提出了一種新的增量式布局方法w - ecop來滿足快速調整布局方案的要求.與以前的以單元為中心的演算法不同，演算法基於單元行劃分來進行單元的插入和位置調整，在此過程中使對原布局方案的影響最小，並且盡可能優化線長.一組從美國工業界的測試例子表明，該演算法運行速度快，調整后的布局效果好
  10. The serializer and deserializer moduls in the ftlvds chip are designed by the way of standard cell design approach. the paper emphatically discusses the tradeoff and the implementation of several clock synchronization modes and circuit structures, and makes a lot of verilog simulation and verification on the circuits designed

    串並模塊串列化器和解串列器採用標準單元的方法設計，論文討論了對幾種時鐘同步模式以及串並轉換電路結構的權衡和實現，並對所設計的電路結構進行了verilog模擬驗證。
  11. Saturated standard cell

    飽和式標準電池
  12. Finally the design of rs decoder in this chip is described as an example of the hardware / software co - design based on asip, the construction and application of asip is also analyzed. the fourth chapter introduces the design flow using eda tools based on standard cell, then it presents the dft of this chip in detail which uses following techniques : full scan, bist and boundary scan to improve the fault coverage

    第四章，在對本晶元的基於標準單元eda設計流程進行了簡要說明基礎上，對本晶元採用的可測試性設計進行了詳細的分析和說明，本晶元中有機結合了多種可測試性設計技術：基於全掃描的方式、 bist測試技術、邊界掃描技術，保證了很高的測試故障覆蓋率。
  13. Permissible cumulative discharge of standard cell

    標準電池允許累計放電量
  14. The thesis discusses how to design a chip, which works as a target pci device, and provides its semi - custom design method based on standard - cell library

    本文研究一種支持pci從設備總線協議的介面晶元的設計方法，並完成了其基於標準單元的半定製asic設計。
  15. Temperature - hysteresis effect of standard cell

    標準電池溫度滯後效應
  16. Unsaturated standard cell

    不飽和式標準電池
  17. The focus of our research in the low - power design of viterbi decoders is reduction of dynamic power dissipation at logic level in the standard cell design environment

    從這里發掘功耗的潛力是很大的，主要通過優化演算法、優化邏輯結構來實現。
  18. Verification regulation of standard cell

    標準電池檢定規程
  19. Permissible discharge of standard cell

    標準電池允許放電量
  20. A new heuristic algorithm based on two equal terminals partition method for standard cell placement

    基於改進等分節點法的啟發式布局演算法
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