standard clock 中文意思是什麼

standard clock 解釋
標準鐘
  • standard : n 1 標準，水準，規格，模範。2 旗；軍旗，隊旗；【徽章】標幟，標記；旗標，象徵。3 【植物；植物學】...
  • clock : n 1 鐘；掛鐘，座鐘，上下班計時計。2 〈俚語〉記秒錶，卡馬表；〈美俚〉〈pl 〉駕駛儀表，速度表，里程...
  1. Maintaining a caesium beam clock as the hong kong time standard and providing time signals for radio broadcasts, automatic telephone answering service and synchronisation of clocks via internet

    操控銫原子鐘作為香港的時間標準，以及透過各電臺自動答覆電話查詢服務及網際網路校對時鐘服務提供報時訊號
  2. Maintaining a caesium beam clock as the hong kong time standard and providing time signals for radio broadcasts, automatic telephone answering service and synchronization of clocks via internet

    操控銫原子鐘作為香港的時間標準，以及透過各電臺、自動答覆電話查詢服務及網際網路校對時鐘服務提供報時訊號；
  3. The hong kong time standard is maintained with a caesium beam atomic clock kept in the observatory

    ：天文臺的銫原子鐘是用來訂定本港的時間標準。
  4. This is the basis for the well-known cesium clock, presently the standard of frequency and time.

    這就是眾所周知的銫原子鐘的基礎，它是目前的頻率和時間基準。
  5. Diesel, high roof, 5 - speed manual transmission, china standard specification, automatic door ( gliding type ), clock, cooler, amfm radio & cassette wmicrophone, tachometer, rear fog lamp, rear under mirror, rear window defogger, curtain, passengers seat belt, baggege rack, full wheel cap, high mount stop lamp, refrigerator. side glasspro - molding

    ，柴油，高頂，五檔手動變速，自動門（飛機門） ，鐘，原廠空調，收錄機連話筒，轉速表，后霧燈，尾鏡，尾發熱線，窗簾，乘客座位安全帶，行李架，大轆cap ，尾高掛剎車燈，冰箱，側面車窗（滑動式深綠色玻璃）
  6. 5 - speed manual transmission, efi gasoline, high roof, high roof 26 seater with passenger seat belt, automatic door ( fliding type ), clock, air conditioner, amfm radio & cassette wmicrophone, rear under mirror, rear window defogger, curtain, baggege rack, full wheel cap, high mount stop lamp, refrigerator, china standard specification

    ，中國規格，汽油，高頂，手動波，飛機門，鐘，原廠空調，收音錄音機連咪，尾鏡，尾發熱線，窗簾，乘客座位安全帶，行李架，大轆cap ，尾高掛剎車燈，電冰箱，排氣規制對應發動機，車尾霧燈，緊急用具（錘子） ，尾輪胎強化
  7. Football ball alarm clock standard lamp

    足球球鬧鐘臺燈
  8. The basketball alarm clock standard lamp

    籃球鬧鐘臺燈
  9. The time base was given both by a crystal clock and the broadcast standard signals.

    時間標準是由石英鐘和廣播標準信號提供的。
  10. Abstract : a new clock - driven eco placement algorithm is presented for standard - cell layout design based on the table - lookup delay model. it considers useful clock skew information in the placement stage. it also modifies the positions of cells locally to make better preparation for the clock routing. experimental results show that with little influence to other circuit performance, the algorithm can improve permissible skew range distribution evidently

    文摘:提出了一種新的時鐘性能驅動的增量式布局演算法，它針對目前工業界較為流行的標準單元布局，應用查找表模型來計算延遲.由於在布局階段較早地考慮到時鐘信息，可以通過調整單元位置，更有利於后續的有用偏差時鐘布線和偏差優化問題.來自於工業界的測試用例結果表明，該演算法可以有效地改善合理偏差范圍的分佈，而對電路的其它性能影響很小
  11. A passionate, global team of open source developers are working around the clock on a standard, certified server that you can download and use freely - with no obligation to contribute back in any form

    在全球范圍，熱心的開放源碼開發人員圍繞著一個標準的經過認證的服務器進行工作，您可以免費下載和使用這個服務器，而不必承擔以任何形式提供回報的義務。
  12. The hong kong observatory ( hko ) uses a caesium beam atomic clock to maintain the hong kong standard time, which is the official time of hong kong

    香港天文臺銫原子鐘提供的香港標準時間，是香港的法定時間標準。市民可以透過網際網路使用天文臺網路時間服務，把電腦時鐘對準香港標準時間（
  13. The concept of " timing " in the article is not the clock in our ordinary living, but syntheses which is made up of some frequency source in the signal generator ( such as cs atom frequency standard, rb clock & high accuracy quartz crystal oscillator ) which produces the primary frequency, the matching input interface and the matching output interface and controlling circuit etc. for example, bits is a kind of timing equipment, which is used to control the timing of some functions

    本文論及的「時鐘」概念不是指日常生活中使用的鐘表，而是由產生基準頻率的信號發生器（如銫原子頻率標準、銣鐘及高精度石英晶體振蕩器等）中的某種頻率源以及相配套的輸入、輸出介面和控制電路等組成的一整套具有特定同步定時功能的綜合體。如bits就是一種時鐘設備，它提供用在通信系統中控制某些功能的定時的時間基準設備，時鐘提供的信號稱為基準信號、定時信號或同步信號。
  14. After analyzing network time protocol and other clock synchronization algorithm, come out with an application of standard time on network, and get out the illustration of system design and realization

    在分析了網路時間協議和其他時鐘同步演算法后，提出了標準時間在網路上的一種應用，並且給出了系統設計和實現的說明。
  15. In the base of investigating and analyzing to working theory, measure methods and relevant standard, the text processes particular analyses to the working theory of billing system and reason of making billing wrong and puts forward technology index and measure method that can externally evaluate the capability of billing system and is suit to the situation of our country. some indexes and measure way are put forward for the first time ( example error of call clock, time error and measure method to moving exchanger ' s billing system. ) through analyzing telecom charging way, charging users, charging point and charging methods of telecom basic and all kinds value - added operation and utilizing the newest measure apparatus, modern measure technology, communication technology and probable method, this text puts more scientific, efficient and easily operated measure methods and process a uncertain analysis to measure methods

    本文在調查和分析國內外局用交換機計費系統工作原理、檢測方法和相關標準的基礎上，對計費系統的工作原理和產生計費錯誤的原因進行了詳細的分析，提出了適合國情的能夠客觀評價計費系統計量性能的技術指標和檢測方法，有些指標和檢測方法在國內相關資料中屬首次提出，如通話計時誤差和時刻誤差和對移動交換機計費系統的一些檢測方法；本文通過對電信基礎業務和各類增值業務的計費方式、計費用戶、計費點和計費方法的分析，利用國內外最新檢測儀器、現代檢測技術、通信技術和概率統計方法，提出了較科學、有效和利於實施的檢測方法，並對檢測結果的測量不確定度進行了分析。
  16. Varification regulation of standard digital clock

    標準數字時鐘檢定規程
  17. This module works with a clock of 40mhz and its input accept lvds signal, output are both in lvds and ecl standard. the setting of the delay parameters is realized with vme software commands

    該插件的工作由40mhz時鐘控制，輸入電平為lvds 、輸出為lvds和ecl電平，其初始化通過vme總線加載，並具有多種編程下載方式。
  18. The serializer and deserializer moduls in the ftlvds chip are designed by the way of standard cell design approach. the paper emphatically discusses the tradeoff and the implementation of several clock synchronization modes and circuit structures, and makes a lot of verilog simulation and verification on the circuits designed

    串並模塊串列化器和解串列器採用標準單元的方法設計，論文討論了對幾種時鐘同步模式以及串並轉換電路結構的權衡和實現，並對所設計的電路結構進行了verilog模擬驗證。
  19. Chapter 2 describes the system part of mpeg - 2 standard with focuses on psi ( program specific information ) and pcr ( program clock reference )

    第二章主要講述了mpeg - 2標準系統層規范，著重介紹節目特殊信息psi和節目時鐘參考pcr 。
  20. An improved high - resolution current - mode sorter is presented. its structure complexity is o ( n ), which is crucial to the expansion of its size, and its dynamic range is large. only one clock signal and one reset signal are needed. no biasing signal is required. the operation point is constructed according to the input current, so it is self - adaptive, which is very important for an all - purpose component. in average value circuit, subtraction circuit, winner - take - all ( wta ) circuit and control circuit, it has good performance even at a large input current. this sorter has high precision, high resolution and low power, as has been proved via hspice simulation. it can be implemented in the standard digital cmos technology and widely used in many fields, so it is of great value in applications

    提出了一種改進的高精度電流型排序電路.它的結構復雜性僅為o （ n ） ，便於擴展;動態范圍大;它是自適應的，工作點由輸入電流確定，故不需要偏置信號，這對作為通用器件使用的排序電路來說是很重要的.通過利用平均值電路、減法電路、 wta電路和控制電路，可以使該電路在大輸入電流下依然保持高性能. hspice模擬表明該電路具有高準確性、高精度、低功耗的特點.它能用標準數字cmos工藝來實現，可以被應用於很多領域，具有很高的應用價值
分享友人
分享到 Line

分享到臉書