superscalar 中文意思是什麼
superscalar
解釋
（超標量體系結構）：在同一時鐘周期可以執行多條指令流的處理器架構。-
19 henry d s, kuszmaul b c, loh g h, sami r. circuits for wide - window superscalar processors. in proc. the 27th annual int
針對具有相同數據路徑的標準多發處理器而言， momr增強的多發處理器提供了更多的加速比。 -
Modem superscalar microprocessors try to perform anywhere from three to six instructions in each stage
現代超標量體系結構的微處理器努力在流水線操作的每一步中完成三到六條命令。 -
Pipelining, superscalar organization and caches will continue to play major roles in the advancement of microprocessor technology, and if hopes are realized, parallel processing will join them
在微處理器技術的發展中，流水線操作、超標量體系結構和高速緩沖內存儲器仍將扮演著重要的角色。如果可能，平行處理方法也會加人。 -
Superscalar risc microprocessor is the further development of reduced instruction set computer, it improve the instruction - level - parallism by means of adding parallel pipelining function units and dynamic on - chip scheduling. this thesis anslysises the architecture and the diversified techniques of superscalar computer
超標量risc微處理器是精簡指令結構（ risc ）的進一步發展，它通過增加并行流水執行單元並結合片上硬體動態調度來提高指令并行度。 -
Both superscalar and scalable, it was more compatible with power1 than later rs64 chips would be
其超量運算能力和可擴展性都很好，與power1晶元的兼容性比后來的rs64晶元都要好。 -
Smpdca architecture has six outstanding excellences : complexity of the control logics of smpdca is lower than large scale superscalar ; supplying shortest inter - processor communication latency using the shared li data cache ; no cost to maintain cache coherence ; hit rate of data cache increase ; easy to reuse many softwares of symmetric multiprocessor ( smp ) ; exploit the parallelism of applications from many levels. this paper present the architecture model of smpdca, and illustrated its function units, and discussed its key techniques, and analyzed the address image policy of multi - ported cache
Smpdca結構具有六個突出優勢：相對于大規模的超標量結構而言， smpdca結構的控制邏輯復雜性明顯要低得多；相對于通過共享主存來實現處理器之間的通信的結構而言，通過一個共享的第一級數據cache來實現處理器之間的通信的smpdca結構能夠提供非常小的處理器之間的通信延遲；沒有cache一致性維護開銷；數據cache命中率提高；便於smp （對稱多處理器結構）的軟體重用；從多個層次上開發程序的并行性。 -
Method and systems are disclosed for exploring instruction - level parallelism in superscalar processors by renaming stack entries
本發明揭露了經由重新命名堆疊記錄之方法與系統裝置，以發掘超純量處理機指令間平行度。 -
Gives techniques for improving the speed of matrix multiplication by more than a factor of two on superscalar risc processors
講述在超標量risc處理器上用大於二的因子來提高矩陣相乘的速度的方法。 -
Based on trace processors, mptp duplicates multiple superscalar processors as processing elements ( pe ), and executes instruction traces in pes
Mptp處理器以trace處理器為基礎，重復設置多個超標量處理單元，把指令流的多條trace發送到處理單元同時執行。 -
In a multithreaded microprocessor which has a superscalar execution core, with the issue width being larger and the pipeline getting deeper, the misprediction penalty will become longer
在執行單元為超標量結構的多線程處理器中，轉移誤預測損失會隨著指令發射帶寬和流水線級數的增加而增加。 -
Nowadays, all of the microprocessor designs are often based on the superscalar technology, which has little room for improving performance more due to its two limitations : hard to realize and low resources utilization
當前的處理器主流技術超標量結構由於實現非常復雜和資源利用率低的缺陷而難以再大幅度提高其性能。 -
With such research background, this dissertation focuses on the research of hardware techniques for thread level parallelism in high performance microprocessors, especially the multithreaded microprocessor which has superscalar execution core
在這種背景下，本文研究支持線程級并行的硬體技術，尤其是執行單元為超標量結構的多線程處理器。 -
Firstly, for the purpose of research and verification of multithread microprocessor, a superscalar microprocessor model armp - v2 is built on the basis of armp microprocessor ; secondly, the issue logic is not only the critical path in a superscalar microprocessor, but also critical to the performance of a multithreaded microprocessor with superscalar execution core
首先，在設計的嵌入式微處理armp的基礎上進行改進，提出了一個超標量處理器模型，用於多線程處理器系統結構的研究與驗證。其次，指令發射邏輯是超標量處理器中的關鍵路徑，也是制約執行單元為超標量結構的多線程處理器主頻提高的關鍵因素。 -
The compiler prearranges the bundles so the vliw chip can quickly execute the instructions in parallel, freeing the microprocessor from having to perform the complex and continual runtime analysis that superscalar risc and cisc chips must do
編譯器預先安排好這種捆綁，因而vliw能快速地平行處理指令，免去了微處理器不得不執行復雜和連續的運行時間分析，而超級標量risc和cisc晶元必須做這種分析。 -
Ieee journal of solid - state circuits, may 1998, 33 : 707 - 712. 18 onder s, gupta r. superscalar execution with direct data forwarding. in proc
我們將證明， momr執行在典型的多發處理器中整合leverages可用的資源，額外成本很小。 -
But because all instructions completed in one clock cycle, it lacked floating - point and superscalar parallel processing ability
但是由於所有的指令都必須在一個時鐘周期內完成，因此其浮點運算和超量計算（并行處理）能力很差。 -
Unlike other risc processors of the day, power1 was functionally partitioned. this gave it superscalar abilities beyond those of mortal chips
與當時其他的risc處理器不同， power1進行了功能劃分，這為這種功能強大的晶元賦予了超量計算的能力。 -
A novel 32 bit embedded fix - point superscalar risc core is developed. then we analysis the power dissipation of risc core from view of instruction - set - architecture, datapath, supply voltage and dynamic power optimization
並從系統層次對risc處理器進行功耗分析，分別從改進指令體系結構、處理器數據通路、降低系統工作電壓和動態降低功耗四個方面進行低功耗研究。
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