synchronization circuit 中文意思是什麼

synchronization circuit 解釋
同步電路
  • synchronization : n. 同時；同時性；【物理學】同步，同期；【電影】同期[步]錄音，配音譯制。
  • circuit : n 1 （某一范圍的）周邊一圈；巡迴，周遊；巡迴路線[區域]；迂路。2 巡迴審判（區）；巡迴律師會。3 【...
  1. In the method of impulsive synchronization, both seriate system and discrete system have been discussed. a series of discrete hyperchaos systems that have the lowest dimension have been constructed, and we have achieved the impulsive synchronization of discrete system in circuit

    脈沖同步法中，分別從連續系統和離散系統兩方面進行討論，構造出一系列具有最低維數的離散超混沌系統，並通過電子線路實現了離散系統的脈沖同步。
  2. The field of video signal processing is now undergoing a digital reform. the digital processing technique is clearly expatiated in this paper, such as a / d convert, anti - alias filter, clamp control, gain control, pll, synchronization circuit, color decoder, comb filters

    本文詳細敘述了視頻圖像的數字處理方法，重點介紹了視頻信號數字化技術、抗混疊濾波器、箝位、增益控制、鎖相技術、同步時鐘產生、電視信號亮色分離、彩色解碼等技術，這些關鍵技術為視頻信號的數字化處理提供了重要的基礎。
  3. Gigabit - ethernet synchronization detector integrated circuit

    千兆以太網同步檢測集成電路設計
  4. In part two, we use a method of the unit of function circuit to structure some hyperchaotic circuits realize the control and synchronization of hyperchaos

    第二部分研究單元功能電路法構造超混沌電路實現超混沌控制和同步。
  5. Based on the analysis of the driving theory of tft - lcd and the characteristic of lvds interface, we designed a drive circuit to control the horizontal / vertical synchronization signals and pixel signal, this drive circuit has a lvds interface. we make and debug the drive circuit by using performance - to - price fpga ep1c3t144 and lvds transmitting chip ds90c387

    在深入分析了液晶顯示器驅動原理和lvds介面特性的基礎上，基於fpga設計了控制顯示器行/場同步信號和顯示像素信號輸出lvds介面的驅動電路，並採用高性價比的fpga晶元ep1c3t144和lvds發送器晶元ds90c387製作和調試了相應的電路。
  6. Bit synchronization circuit design for digital communication system

    數字通信系統位同步電路設計
  7. In chapter 4, the circuit of the carrier synchronization unit is implemented on fpga, the resistor transistor logic ( rtl ) schemes are presented

    第四章在fpga平臺上實現載波同步單元電路，並給出了實現后的fpga資源消耗、寄存器傳輸邏輯（ rtl ）原理圖。
  8. Secondly the detection precision is only related to the synchronization phase but not to the amplitude of the mainline voltage because that it uses the optimized pulses synchronous with the mainline voltage as modulation signals. thirdly it decreases the requirement of the input low pass filter and eliminates the error resulting from the direct component and even harmonics of load current. the most significant merit is that it can eliminate the effect of a few low order odd harmonics and the detecting circuit is easy to be implemented

    模擬和實驗結果表明該方法的主要優點有：不需使用乘法器進行信號調制，調制信號採用與電網電壓同步的優化特定脈沖，其檢測精度只與同步相位有關，而與電網電壓幅值無關；降低了對輸入低通濾波器的通頻帶要求，直流和偶次諧波分量對檢測精度沒有影響；突出的優點是可以消除有限個低奇次諧波對檢測結果的影響。
  9. The main circuit is consisted of 18 thyristors circuit and protection circuit. with the help of control subsystem, it can get the output of low frequency voltage ( current ) with the shape of sine wave ; the core of the control subsystem is the cpu of 87c196kc, and the synchronization circuit, the pulse - widen circuit, and the power - enlarged circuit form the accessorial subsystem of the control system. it possesses all the functions of digital triggering, digital tuning, analog / digital conversion ; the input transfer can isolate the input and output ; and the circumfluence reactor can reduce the circumfluence

    主迴路採用由18個晶閘管組成的三相零式電路，並輔以晶閘管的保護電路，通過控制可以得到低頻正弦波的電壓（電流）輸出；控制迴路主要以87c196kccpu為核心，其外圍電路包括同步電路，脈沖拓寬電路，功率放大驅動電路等，完成了數字觸發、數字調節、模數轉換等功能；進線電源變壓器具有變壓和隔離作用；環流電抗器則實現了有效抑制主迴路瞬時脈動環流的功能。
  10. The whole circuit ' s timing generation and synchronization was realized with cpld. as the channel of data transmitting, pof can isolate high voltage part and low voltage part efficiently. at the same time, a single chip processor was used to design a digital meter for the fiber current transducer

    系統採用cpld實現整個工作電路的時序發生和同步協調，利用光纖實現高壓部分和低壓部分的完全電氣隔離和實現信號傳輸，採用單片機技術實現混合式光纖電流互感器專用數字顯示儀表的設計。
  11. Finally, flexible programming gate arrays ( fpga ) based circuit frameworks for main components of ofdm synchronization are given

    最後基於現場可編程門陣列（ fgpa ）實現給出了ofdm同步主要模塊的電路結構。
  12. Then, according to the execution of dispatching list, automatically revise circuit material and data synchronization and the circuit dispatch conditon can be tested according to dispatching list

    然後根據調度單的執行情況，自動對電路資料進行修改和數據同步，並能根據調單執行情況統計考核電路調度任務的執行情況。
  13. The circuit of assembling frame and splitting frame based on ram and fifo are designed ( realized frame synchronization ). the two 3b4b converting circuits are designed ( realized one circuit ). the nrz, rz, manchester code converting circuits are designed

    4 、設計了基於fifo和ram的兩種組幀和拆幀電路（實現了幀同步碼檢出） ；設計了兩種3b4b編譯碼電路（實現了一種） ，針對nrzi 、 rz和曼碼各設計了一個編譯碼電路。
  14. The clock obtaining practical circuit in approximately synchronization and clock circuit about symbol synchronization are designed ( realized one circuit ) ; the three controlling circuits with fast and low clock in code speed adjust technique are designed

    在此基礎上設計了基於scc準同步的一種時鐘恢復實現電路和兩種字元型起止式同步電路（實現了一種） 。設計了正碼速調整技術中快慢時鐘的三種控制電路。
  15. The serializer and deserializer moduls in the ftlvds chip are designed by the way of standard cell design approach. the paper emphatically discusses the tradeoff and the implementation of several clock synchronization modes and circuit structures, and makes a lot of verilog simulation and verification on the circuits designed

    串並模塊串列化器和解串列器採用標準單元的方法設計，論文討論了對幾種時鐘同步模式以及串並轉換電路結構的權衡和實現，並對所設計的電路結構進行了verilog模擬驗證。
  16. Associated with the research project, the author has done some research on the synchronization issues in utran and the synchronization methods used in ip networks to transport circuit emulation services ( ces )

    本文結合科研項目的需要，對第三代移動通信系統陸地無線接入網（ utran ）中的各種同步問題以及全ip網路中傳送電路模擬業務的同步方法進行了比較深入的研究。
  17. The control system includes two modules, one named the input module which acquires data digitally, and the other, named the output module, controls the emission of the laser, the gating function of the single photon counting module ( spcm ) and the synchronization of the input and output modules. each of them uses a complex programmable logic device ( cpld ) as the core component, and is devided into three parts : the hardware circuit, the programming logic circuit and the software

    該控制系統主要包括控制單光子發射、單光子探測器、數據採集接收系統的輸出系統和數據採集系統兩個模塊，它們都採用復雜可編程邏輯器件cpld作為核心功能晶元，由硬體電路設計、晶元編程和高級軟體編程三部分組成。
  18. Qe1 achieve the whole synchronization by software and hardware. during the course of the initialization of the qe1 system, the chip pm4354 can accomplish the task of synchronization of bit, frame and multiframe after the chip initialization by the software. after pm4354 accomplishes the bit synchronization, qel will read the status registers of the pm4354 to get the status of each el circuit and choose recovered clock of the specified the el circuit as the external timing source of the whole htc - 5200an equipment

    Qe1系統在系統初始化時，通過軟體完成對硬體晶元pm4354的初始化工作后，便可利用該晶元完成4路e1的同步（位同步、幀同步和復幀同步） ；在pm4354完成時鐘提取的任務后， qe1通過不斷地訪問pm4354的狀態寄存器，獲得每路e1的狀態信息，在時鐘源的選擇原則下，選擇指定e1線路的恢復時鐘作為整個htc - 5200an節點設備的外部參考時鐘，從而解決了htc 5200an的中繼板卡由e1變為qe時所帶來的網同步時鐘源。
  19. With the current condition, the paper raises the point of synchronization in the qe1 ' s development, including the synchronization of bit, frame, multiframe and network and analyses the performance frame synchronization system based on the theory of probability and finally explains the realization of the technology of synchronization. the hardware circuit diagram of qe1 and some software flow chart have been offered in the paper

    在針對qe1中繼板卡系統實際的開發情況后，本文分析了該系統所涉及的同步問題（包括位同步、幀同步、復幀同步和網同步） ，在概率論的基礎上分析了qe1系統的幀同步系統的性能，並研究了各種同步技術在qe1中的實現。
  20. The 4d oscillator circuit is simple and easy to realize in reality, which shows complicated dynamic character, and it is a hyperchaotic system, it will show great value to study and research the synchronization and control of this hyperchaotic system

    四維l . c振子電路系統結構簡單，具有復雜的動力學行為，是一個超混沌系統，對該系統進行同步與控制的研究將具有潛在價值。本文針對這個模型做了以下工作。
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