synchronization clock 中文意思是什麼

synchronization clock 解釋
同步時鐘
  • synchronization : n. 同時；同時性；【物理學】同步，同期；【電影】同期[步]錄音，配音譯制。
  • clock : n 1 鐘；掛鐘，座鐘，上下班計時計。2 〈俚語〉記秒錶，卡馬表；〈美俚〉〈pl 〉駕駛儀表，速度表，里程...
  1. Maintaining a caesium beam clock as the hong kong time standard and providing time signals for radio broadcasts, automatic telephone answering service and synchronization of clocks via internet

    操控銫原子鐘作為香港的時間標準，以及透過各電臺、自動答覆電話查詢服務及網際網路校對時鐘服務提供報時訊號；
  2. The tft lcm driver signals were enable signal and fiducial clock signal, which were strict with synchronization

    驅動信號主要為使能信號和基準時鐘信號，並要求二者具有嚴格的同步性。
  3. A new method for clock synchronization of meo satellite

    衛星星地時間同步的新方法
  4. As concerning to the interference condition between different transmit / receive channels in the system, a detailed error analysis is given, and the clock and synchronization scheme is explicated. the measure adopted to enhance phase clock ' s precision is explained

    本文對超聲相控陣系統中各通道發射/接收的相干條件進行了詳細的誤差分析，闡明了本系統採用的時鐘和同步方案，以及改進相控陣時鐘精度的方法。
  5. The site for synchronization of your computer clock

    這個校對電腦時鐘網頁
  6. Fist, quick bit synchronization. the common methods are relative synchronization, multi - phase clock sample and so on

    第一，快速比特同步。常規的方案有相關同步法和多相位時鐘采樣法等。
  7. To achieve fast acquisition with only a few symbols, a joint structure for clock and carrier synchronization with non - data aided ( nda ) mode is presented

    摘要為了實現解調中的快速同步，本文給出了一種聯合結構下無數據輔助載波同步和符號同步的方法。
  8. After analyzing network time protocol and other clock synchronization algorithm, come out with an application of standard time on network, and get out the illustration of system design and realization

    在分析了網路時間協議和其他時鐘同步演算法后，提出了標準時間在網路上的一種應用，並且給出了系統設計和實現的說明。
  9. Using an 8 - depth async fifo solves the synchronization and exchange of data be - tween different clock domains. the data transaction protocol comes from the most basic work way of uart. when the master clock is 16. 7mhz, the pcm side and adpcm side clocks both are 2. 38mhz, the results of simulation show that the latency from the start - bit of pcm data inputting uart receiver to the stop - bit of adpcm data outputted uart transmitter is 14. 3 us and the latency from the start - bit of adpcm data inputting uart receiver to the stop - bit of pcm data outputted uart transmitter is 14. 7 us

    在主時鐘為16 . 7mhz ， pcm數據端與adpcm數據端時鐘均為2 . 38mhz時，模擬結果表明從pcm的起始位輸入uart接收器到adpcm終止位輸出uart發送器的最大延遲為14 . 3 s ，從adpcm的起始位輸入uart的接收器到pcm終止位輸出uart發送器的最大延遲為14 . 7 s ，設計時盡可能的使編碼與解碼的時間相差不多，從結果看出基本達到這個要求。
  10. The theoretic basis and the dat agram format of the newly propounded rts method are presented. finally, in the protocol stack of ip over ethernet, after the analysis of plesiochronization method and external clock method, a new synchronization method of absolute time stamp ( ats ) method is put forward, and detailed discussion is presented in this thesis

    針對物理層不能提供同步的情況（如ipoverethernet ） ，本文在分析基於外部同步信息的準同步法和外同步法以及基於業務碼流的自適應時鐘法之後，提出了一種新的絕對時標法，並對該方法的實現進行了較為詳細的研究。
  11. Experimental results suggest that the multi - hop error accumulation of the clock synchronization algorithm is reduced after data fusion

    試驗數據表明，數據融合后時鐘同步演算法中的多跳誤差累積得到明顯降低。
  12. Chongqing expressway networking toll data communication network cotains 2 - ring and 8 - ray network structure based on expressway physical structure, setting up a trasmission trunk layer of sdh stm - 4 ( can be up - graded to stm - 16 ), and channel protection business entry layer consisting of sdh onu / olt stm - 1 ( can be up - graded to stm - 4 ). data exchange layer, through ip route exchange network above sdh network, forms 3 - level computer network structure of account settlement center - road section management company - toll station. to ensure obtaining original and reliable toll data from communication network, 2m circuitous chain is established between each toll station, accountsettlement center and road section management company, and also pstn dialing backup chain is set up between toll station and account settlement center. in order to maintain clock synchronization of the whole communication network, a proposal of sub - stage clock sychrononization signal network for differet network construction scale has been put forward in this design. in view of sensitivity and importance of toll data, this design particularly gives considerations of network safety and information safety for external and internel of network. therefore, communication safety, smoothness and reliability of networking toll system can be able to maintained in many ways

    重慶高速公路聯網收費數據通信網的結構是根據高速公路的物理結構構築了2環8射的網狀結構，建立了以sdhstm - 4 （可升級到stm - 16 ）的傳輸主幹層，以sdhonu / oltstm - 1 （可升級到stm - 4 ）組成的通道保護業務接入層。數據的交換層是在sdh網之上的ip路由交換網，形成了結算中心-路段管理公司-收費站之間的3級計算機網路結構。為從通信網路上保證收費數據的原始性和可靠性，每個收費站和結算中心、路段管理公司之間建立了2m迂迴鏈路，同時在收費站和結算中心之間建立了pstn的撥號備份鏈路。
  13. The equilibrium thermal radiation in a flat space - time or a curved space - time behaves like planck black spectrum represented with coordinate quantities. we regard the fact that the radiation from a thermal equilibrium system shows planck black spectrum as a basic physics law, from which it is demonstrated that the transitivity of clock rate synchronization is equivalent to the zeroth law of thermodynamics. the condition of clock rate synchronization is weaker than that constructing simultaneity surfaces. in the space - time satisfying the condition of clock rate synchronization, the zeroth law of thermodynamics is valid. on the other hand, in the space - time where the zeroth law is valid, one can define an identical clock rate

    平直或彎曲時空中的平衡熱輻射，表現出用坐標量表示的普朗克黑體譜.把熱平衡系統的輻射具有普朗克黑體譜作為一條基本的物理規律，以此為基礎，論證鐘速同步的傳遞性等價于熱力學第零定律.鐘速同步的條件比建立同時面的條件要弱.滿足這一條件的時空，熱力學第零定律在其中成立.第零定律成立的時空，一定可以定義統一的鐘速
  14. Requirements for clock and synchronization equipment used in the digital network

    數字網內時鐘和同步設備的進網要求
  15. The clock obtaining practical circuit in approximately synchronization and clock circuit about symbol synchronization are designed ( realized one circuit ) ; the three controlling circuits with fast and low clock in code speed adjust technique are designed

    在此基礎上設計了基於scc準同步的一種時鐘恢復實現電路和兩種字元型起止式同步電路（實現了一種） 。設計了正碼速調整技術中快慢時鐘的三種控制電路。
  16. The serializer and deserializer moduls in the ftlvds chip are designed by the way of standard cell design approach. the paper emphatically discusses the tradeoff and the implementation of several clock synchronization modes and circuit structures, and makes a lot of verilog simulation and verification on the circuits designed

    串並模塊串列化器和解串列器採用標準單元的方法設計，論文討論了對幾種時鐘同步模式以及串並轉換電路結構的權衡和實現，並對所設計的電路結構進行了verilog模擬驗證。
  17. Node clock set of digital synchronization network and its timing feature

    數字同步網節點時鐘系列及其定時特性
  18. Cdma2000 bts clock synchronization system and circuits

    2000基站時鐘同步系統及電路
  19. A clock synchronization algorithm for distributed real time systems

    一種分散式實時系統中的時鐘同步演算法
  20. A high precise gps glonass synchronization clock pll

    同步時鐘鎖相環
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