systolic array 中文意思是什麼

systolic array 解釋
脈動陣列
  • systolic : 脈動陣列
  • array : vt 1 打扮,裝飾。2 使…列隊,排列。3 提出(陪審官)名單,使(陪審官)列席,召集(陪審官)。n 1 整...
  1. The improved algorithm not only inherits the fast convergence trait from rls and realizable systolic array from qr _ rls, but also eliminates square - root operation and gets directly equalizer output signals from systolic array. so this algorithm has more simple operation, faster executing speed, less hardware resource and lower hardware cost. some different equalization algorithm are imitated on the qpsk communication system with multipath channel

    其次對一些成熟的自適應均衡演算法(如lms演算法、 rls演算法、 qr _ rls演算法、逆qr _ rls演算法)進行了分析;介紹了一種改進后的無平方根的qr _ rls演算法,該演算法不但繼承了rls的快速收斂特性和qr _ rls演算法的systolic陣列可實現性,還取消了qr _ rls演算法的平方根運算,使演算法在硬體實現時運行速度更快,佔用資源也更少,同時該演算法還可由systolic陣列直接得到均衡后的輸出信號,運算量更小。
  2. Rsa cryptoprocessor based on a redesigned systolic array

    基於新型脈動陣列的rsa密碼處理器
  3. Since the filtering vector is needed in qrd - rls and qrd - brls, the parallelism of qr decomposing will be impeded slightly. the inverse qr decomposion ( iqrd ) scheme for brls algorithm is proposed in this dissertation to enhance the parallelism, the systolic array structure for iqrd is proposed to calculate the algorithm in parallel

    鑒于碼輔助最優濾波需要求解濾波權值矢量,此時qr分解的計算并行性不如逆正交三角分解( iqrd ) ,本文提出了基於iqr分解的brls演算法,給出了iqrd - rls / brls的脈動陣列并行計算結構。
  4. Improve on algorithms can enhance encoding / decoding performance. with pipeline and systolic array architectures adopted in the hardware implements, encoder / decoder based on fpga can work better

    對編譯碼演算法的改進有助於提高rs編譯碼器的性能,而利用fpga來實現rs編譯碼器,並採用流水線、心縮式陣列等優化結構,更能提高編譯碼器的性能。
  5. For intra prediction, the boundary pixels are reshuffled before feeding into the systolic array

    對于內部預測,我們先將邊界點重組后在丟入過濾器中。
  6. To increase hardware utilization and minimize cost, we combine inter and intra prediction by a reprogrammable fir filter, which is further implemented with systolic array

    利用在解碼的過程中一個巨塊不會同時利用到內部以及相互預測的特性,設計了一套既可以處理內部預測也可以處理相互預測單一硬體架構來增加硬體使用效率以及降低成本。
  7. 7 wang c l, lin j l. systolic array implementation of multipliers for gf. ieee trans. circuits and systems ii, 1991, 38 : 796 - 800

    在有限場的各種運算之中,以加法運算最為簡單,而以乘法指數及找乘法反元素等運算較為復雜。
  8. Raac - rsa adopts improved systolic array to realize montgomery arithmetic and, in this way, finishes the cardinal arithmetic of rsa, i. e. multiple module

    其中raac - rsa方案採用改進后的systolic陣列來實現變種的蒙哥馬力演算法,進而完成rsa的核心運算? ?乘模運算。
  9. A novel and generic approach is presented to the hardware implementation of the rsa cryptoprocessor in deep submicro technology with a redesigned systolic array

    長比特1024位以上數據的全局信號傳輸和乘法器的動態分割問題,對于rsa密碼處理器的速度提高是非常重要的因素。
  10. This paper revealed an optimized strategy to search for systolic array transformations for nested loops, when the upper and lower bound of inner index was affine functions of there outer loop indexes

    對于多重循環中,當內層迭代的上下界為外層迭代的仿射函數時,介紹了搜索脈動變換的一個優化策略和相應的自動化演算法。
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