transistor circuit 中文意思是什麼

transistor circuit 解釋
晶體管電路
  • transistor : n. 【無線電】晶體（三極）管；晶體管[半導體]收音機。 a transistor radio 晶體管[半導體]收音機。
  • circuit : n 1 （某一范圍的）周邊一圈；巡迴，周遊；巡迴路線[區域]；迂路。2 巡迴審判（區）；巡迴律師會。3 【...
  1. The modern successor to the transistor is the integrated circuit.

    晶體管的現代后繼者是集成電路。
  2. A complementary input stage, which consists of a p - channel pair and a n - channel pair, was used in the circuit, so that the common mode input range can extend from rail to rail. a dcls is used to shift the n - transistor curve leftward to overlap the p - transistor curve properly and keep constant transconductance in the whole common mode input range

    輸入級採用pmos差分輸入對和nmos輸入差分對並聯的結構，從而實現共模輸入范圍擴大到電源的正負兩端，並且通過兩個源級跟隨器平移nmos輸入管跨導曲線，使nmos輸入管和pmos輸入管跨導曲線的適當交疊，從而保持了這個輸入級的跨導在整個共模輸入范圍內保持恆定。
  3. The main loop of the welder uses a thyratron transistor non - contact switch circuit, quick and reliable close time, accurate timing of welding, high precision of welding, good repeatability, bring a high quality welding

    焊機主迴路採用晶閘管無觸點開關電路，關斷時間快、可靠，焊接定時精確，焊接精度高，重復性好，可實現高品質焊接。
  4. In the case of layout design, discussed the effect and application of the transistor matching in the circuits design deeply. demonstrated the circuit layout check by lvs design

    在電路的版圖設計方面，較深入地討論了晶體管的匹配在電路版圖設計中的作用和應用，通過lvs對電路的版圖檢查進行了具體說明。
  5. Jessi 0. 8m cmos transistor model for analogue and digital circuit simulation

    模擬和數字電路模擬用jessi 0 . 8m cmos傳輸模式
  6. The level adjustment circuit 100 lowers the clock signal input to the first clock terminal ck1 by a predetermined value from h level and provides the signal to the gate of the transistor q5

    電平調節電路100將送往第一個時鐘終端ck1的時鐘信號從h電平降低一個預定值，並將此信號送往晶體管q5的輸入端。
  7. Interconnection dimensions become the limitation for new performance design while the size traditional transistor has met the demand of challenge. thus, the study of interconnection delay becomes more important for current circuit design and technology

    為了提高ulsi的頻率特性，按比例縮小晶體管的特徵尺寸的努力受到了互連線本徵特性和寄生效應的限制，互連線的rc延遲成為ulsi進一步提高頻率特性的瓶頸。
  8. Circuit board, integrated circuit, resistor, capacitor, chips, rectifier, led, diode, transistor, laser pick - up head and all kinds of electronics component

    電路板集成電路電阻電容主晶元整流管發光管二極體三極體鐳射光頭等各類電子零件
  9. The transistor amplifiers, which are the building blocks from which op - amp integrated circuit are constructed, will be discussed

    我們將對構成運算放大器的基本部件：晶體管放大器進行討論。
  10. A lcc multi - resonant ( mr ) network is added to the traditional three - level converters to realize zvs. the unique arrangement of a multi - resonant network results in absorption of all major parasitic components hi the resonant circuit, such as transistor output capacitance, diode junction capacitance and transformer leakage inductance, which can eliminate parasitic oscillation in the converter

    它的優點在於諧振電容吸收了開關管和續流二極體的結電容，諧振電感吸收了變壓器的漏感，使得開關管和續流二極體都能在軟開關的條件下完成導通和關斷過程，消除了電路中的寄生振蕩。
  11. In chapter 4, the circuit of the carrier synchronization unit is implemented on fpga, the resistor transistor logic ( rtl ) schemes are presented

    第四章在fpga平臺上實現載波同步單元電路，並給出了實現后的fpga資源消耗、寄存器傳輸邏輯（ rtl ）原理圖。
  12. Based on many other circuit formats, a new kind of logic - level circuit representation, called unified middle - level circuit format ( umcf ), is defined in this paper, in which some special operations on circuit related with power estimation and low power design. umcf can not only interchange circuits of different formats, but also convert circuits to hspice acceptable files, which can be used for transistor level power estimation

    本文結合多種不同的電路格式，自主定義了一種邏輯級電路的中間表示形式（稱為umcf ）和一系列極具特色的與低功耗技術相關的操作，它不但可以實現與其他多種電路格式之間的相互轉換，還可以將電路直接轉換成hspice可以接受的文件，進行晶體管級的電路功耗估計，這樣可以在公認的高精度的功耗模擬器上，對本文的結果進行有效的驗證。
  13. Thirdly, the paper researchs the application of single electron transistor and the synthesis theory of cicuit based on quantum dot cellular automata by synthesis example of quantum cellular neural network based on build schr ? dinger equation of coupling quantum dot. at last, the paper researchs digital integrated circuit design based on quantum dot cellular automata and design a 8 - bit quantum dot cellular adder by qcadsign based on a method of majority logic reducetion for quantum cellular automata, it prove this designer of 8 - bit quantum dot cellular adder is correctly

    Dinger ）方程為基礎的量子點細胞自動機電路綜合理論，本文以量子細胞神經網路為綜合實例，建立耦合量子點的薛定鄂（ schr ? dinger ）方程組，通過化簡得到類似細胞神經網路的非線性電路方程。最後研究了基於量子點細胞自動機數字集成電路設計，通過建立邏輯方程，簡化邏輯方程，並設計基於精簡qca擇多邏輯門8位加法器，並用qcadesign進行了模擬，實驗證明設計正確性。
  14. Remember the following words and expressions : e. g. multimeter ； circuit ， current ； voltage ； resistance ； digital multimeter ； analogue multimeter ； analogue multimeter scales ； zero adjustment control ； zero adjustment control for resistance ranges ； measurement ranges switch ； transistor test socket ； meter probe ； positive terminal ； negative terminal ； anode ； cathode ； red lead ； black lead ； power supply ； connect in parallel ； connect in series

    記住萬用表、電路、電流、電壓、電阻、數字萬用表、模擬萬用表、表頭、機械零位調整器、歐姆零位調整器、量程選擇開關、晶體管插孔、表棒、正接線端、負接線端、陽極、陰極、紅導線、黑導線、電源、並聯、串聯等常用英文單詞，並逐步掌握。
  15. After introduction of the tranlinear loop principal, the bjt current controlled conveyor has been designed by using mixed tranlinear loop voltage follower. as for modern integrated circuit, the model of mos transistor, the active resistance and the current mirror integrated circuit formed by mos transistor are introduced. the cmos current controlled conveyor has been derived from mixed tranlinear loop cmos voltage follower based on weak inversion operation

    針對現代集成電路的工藝，本文對mos晶體管的工作原理進行了簡要的敘述，討論了有源電阻和電流鏡的實現方法，並利用mos晶體管的亞閾值特性組成混合跨導線性迴路完成對應的電壓跟隨器的設計，推導出了基於cmos技術的電流控制傳送器。
  16. To cancel the offset - voltage of the comparator, a switch capacitance circuit is used between the three pre - amplifier stages. the charge pump circuit is used to boost the clock voltage of the switch transistor

    採用電荷泵電路提供開關管柵過驅動電壓，帶隙基準電路作為電荷泵穩定電壓的輸入，有利於改善開關電路的性能。
  17. The paper are investigating several alternatives for example quantum dot cellular automata and single electron transistor to substitute conventional field effect transistors ( fet ’ s ) for ultra large scale integrated circuit ; and i take research on the modeling of single electron transistor and single electron cicuit

    基於以上考慮，本文研究一些新的基於量子力學原理的器件如量子點細胞自動機（ qca ） 、單電子晶體管（ set ）取代以fet器件為基礎超大規模集成電路，主要在單電子晶體管建模和單電子電路綜合做了一些研究工作。
  18. It is used to normal precise measure and measure equipment, temperature compensation of transistor circuit

    用於一般精度的溫度測量和在計量設備，晶體管電路中的溫度補償。
  19. Cascode transistor circuit

    串聯晶體管電路
  20. Complementary transistor circuit

    互補晶體管電路
分享友人
分享到 Line

分享到臉書