unit cache 中文意思是什麼

unit cache 解釋
高速緩沖存儲器單元
  • unit : n 1 個體，一個，一人。2 （計值、組織、機構）單位；單元；小組，分部；【軍事】部隊；分隊。3 【機械...
  • cache : n. 1. （探險者等貯藏糧食、器材等的）暗窖，密藏處。2. 貯藏物。3. 【計算機】高速緩沖內存。vt. 1. 貯藏；密藏；窖藏。2. 【計算機】把…儲存到硬盤上。
  1. The control system included the following units : video decode unit, data format conversion unit, fpga controller, cache unit and d / a monitor. the above self - design control unit plus row and column power supply units make the whole fed driving system, thus drove the 25 inch sample and realized color video display. the 25 inch vga sample thus fabricated could display video images, and obtained its brightness 400cd / m2, contrast ratio 1000 : 1, 256 circuit gray scale

    本文介紹了fed驅動系統的工作原理，重點論述了基於fpga的vga級彩色fed新型驅動控制系統的研製，這種新型fed驅動控制系統主要包括視頻解碼電路、數據格式轉換電路、 fpga控制電路、數據緩存電路和d / a監控電路，配合后級列灰度調制單元和行掃描單元，組成完整的fed驅動系統，可以驅動25英寸vga級fed顯示屏，實現彩色視頻顯示，樣機亮度達400cd / m2 、對比度為1000 : 1 ，灰度等級為256級。
  2. Jx5 is a complex microprocessor, which contains cache, microcode rom, instruction prefetch unit, instruction decode unit, integer unit, mmx unit, floating point unit, page unit, bus unit, dp logic, apic and so on. it is very difficulty to test a such complicated microprocessor and receive anticipative fault coverage ratio. so, we must add dft in cpu ’ design

    Jx5微處理器是一款結構異常復雜的微處理器，它的內部包含有: cache 、微碼rom 、指令預取部件和動態分支預測部件、指令譯碼部件、整數部件、多媒體部件、浮點部件、分段和分頁部件、總線介面部件、雙處理器介面部件、可編程中斷控制部件等。
  3. There are five parts in powerpc603e ? microprocessor : integer execution unit, floating point unit ( fpu ), instruction ( data ) cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way

    Powerpc603e微處理器系統由定點執行單元、浮點單元、指令（數據） cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令。
  4. It has five parts, such as integer execution unit, floating point unit ( fpu ), instruction cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way. the instruction set and i / o signals are compatible with powerpc

    它由定點執行單元、浮點單元、指令cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令，指令集和介面時序兼容powerpc ，是典型的risc微處理器結構。
  5. Novel stack cache architecture and data - forwarding mechanism between it and the execution unit are also presented. the relationship between the capacity and the backup frequency of the stack cache is analyzed too

    文中還設計了一種由多體靜態存儲器構成的堆棧緩沖結構，並在堆棧緩沖和執行部件之間採用了數據重定向技術，還對緩沖容量和後援頻度的關系進行了理論分析。
  6. The content of the electricity transforming of the system with profibus includes the designing of signal detecting and dealing system, the developing of the major cache unit machine control, the integration of the system diagnosis and data information, and the subordinate station diagnosis function

    基於profibus現場總線技術的濾棒儲存輸送系統電氣改造設計內容，主要從系統信號檢測與處理方式的改進設計、主體緩沖單元電機控制方式的改進設計、系統診斷及生產過程數據信息的集成設計和系統從站診斷功能設計等幾個方面講解。
  7. You might consider forbidding two requests from occurring in the same unit of time, and cache information about what valid requests have arrived in the past 60 seconds

    您可能會考慮禁止在同一時間單元發生兩次請求，並緩存關于過去60秒以內到達的有效請求的資訊。
  8. The packet unit has a queue into which fetched cache blocks are stored containing instructions

    封裝單元中具備了一個佇列，用以儲存讀取到的資料。
  9. Assemblies are added and removed from the global assembly cache as a unit ; that is, the files that constitute an assembly are always installed or removed together. windows installer uses a two - step transactional process to install products containing assemblies, which enables the installer to roll back unsuccessful installations

    將程序集添加到全局程序集緩存中以及將其從全局程序集緩存中移除時，總是將程序集作為一個整體處理；即組成程序集的文件始終是一起安裝或移除的。
  10. Cache memory is constructed with high - speed static random access memory ( sram ), managed in a unit called cache line

    當cache中保存著cpu要讀寫的數據時， cpu直接訪問cache 。
  11. In the 4th chapter, we discuss the problems in the implement of the web service based distributed file service system. it focuses on four problems : the design of central control unit, the policy of mass storage in local file service unit, the parallel access control algorithm and hierarchical cache management mechanism

    論文的第四部分介紹了基於webservice的分散式文件服務系統在應用實現中需要考慮的許多方面的問題，構造出針對四個方面問題的演算法模型：集中控制單元設計模型、海量文件的本地存儲策略、文件並發訪問控制演算法和分層的緩存管理機制。
  12. In order to solve the problems about unfixed instruction length, stack - orientation and addressing virtualization in jvm instruction set, the instruction fetch unit, stack cache and mechanism of address translation in java chip system are studied

    為了解決java虛擬機指令系統中指令不定長、面向堆棧和地址虛擬化等問題，本文研究了java晶元中取指部件、堆棧緩沖部件和地址轉換機制以及相應物理存儲器的管理等關鍵技術。
  13. The power2 added a second floating - point unit and more cache

    Power2晶元中新加了第二個浮點處理單元（ fpu ）和更多緩存。
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