unit processor 中文意思是什麼
unit processor
解釋
單處理機-
Control unit of tcp ip processor with microgram
協議處理器的控制 -
In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future
第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga -
3 - d graphics on mobile phones is quite similar to 3 - d graphics on pc in years past. there is no hardware acceleration, and processor speeds are quite low, and there also is the lack of floating point arithmetic unit in mobile phones
因此論文從通用的部分開始論述，然後明了移動平臺的特徵，並試圖解釋三維引擎的一般原理和設計一個具有粗適性的基於游戲的三維圖形引擎。 -
The integer unit of leon2 embedded processor, published as open source, acts as the processor of this system, which we must further configure for our needs
系統的處理器採用開放源代碼的leon2整數運算器，我們根據mp3播放的需要對其進行配置修改。 -
A processor is composed of two functional units ? a control unit and an arithmetic / logic unit ? and a set of special workspaces called registers
處理器由兩個功能部件（控制部件和算術邏輯部件）與一組稱為寄存器的特殊工作空間組成。 -
In a computer, a functional unit that interprets and executes instructions. note : a processor consists of at least an instruction control unit and an arithmetic and logic unit
計算機中，解釋並執行指令的一種功能單元。注：處理器至少包含有一個指令控制器和一個算術與邏輯運算器。 -
On the one hand it is important for the design of floating - point processor unit to optimize speed while algorithms of high - speed are introduced. for examples, two - path of high - speed floating - point addition, booth coding of floating - point multiplication. srt of floating - point division and square root, cordic of transcendental function and so on
一方面浮點處理部件設計重點在於速度的優化，所以採用優化的高速演算法，如浮點加法的two - path 、浮點乘法的booth編碼、浮點除法和平方根的srt演算法以及超越函數的cordic演算法等。 -
A processor architecture is disclosed including a fetcher, packet unit and branch target buffer
母案摘要:揭露一種包含指令取器、封裝單元及分支目標緩沖器的處理器架構。 -
Measure and control unit adopted 16 - bit, high - speed a / d converter, it can guarantee the speed and precision of alternating sample. the part of communication adopted can bus to transmit the data, it was suitable for real - time control and can guarantee dependability. it adopted the can bus adapter of yan - hua company whose type was pcl - 841 to communicate with processor unit the processor unit adopted industrial pc, which can guarantee the system work well for a long time
其中下位裝置採用西門子公司的高性能十六位處理器c167cr - lm ，其內嵌can總線控制器便於通過can總線與上位機進行通訊，數據採集部分採用十六位高速a d轉換器從而保證了交流采樣的速度與精度，通訊部分採用可靠性高，適于現場實時控制的can總線來傳輸數據，與上位機介面採用研華公司的型號為pcl - 841的can總線適配器，為保證系統長時間可靠運行上位機採用工控機。 -
Amex86 microprocessor is composed of integer processing unit, float - point processor unit ( math coprocessor ) and protect test unit
Amex86系統由一個整數處理部件（ cpu ） 、一個浮點處理部件（數學協處理器）和一個保護測試單元組成。 -
A co - processor - unit has been implemented for convolution in image processing coupled with host with isa, which is directly accessed by system function call
數學協處理器與asp公用一個可重構邏輯資源，由x86主處理器分時異步地重構為不同的專用部件。 -
The author designed and developed a single phase mid - frequency inverter control unit, which is based on dual micro - processor system. the inverter is modulated by pre - set spwm pulse width wave
本文研製出一種基於雙微處理器（ mpu ）控制的單相中頻逆變電源控制裝置，逆變電路基於開關預置spwm波脈寬調制。 -
Taking the single chip processor at89c51 as the run control unit, the device can automatically monitor the whole course of the sit up
它以at89c51單片機作為整機的運行控制部件，達到對仰臥起坐全過程的自動化處理。 -
Based on the theory model of quantum computing and the quantum computing technique in existence, we have proposed the cooperating architecture of quantum computer. in this architecture, it uses the classic processor as its control unit, and use the quantum arithmetic logical unit and quantum memory unit as its co - process unit
針對這種情況，通過對量子計算技術的深入研究，全面剖析現有量子計算系統，借鑒經典計算機中的研究成果，作者提出了協同量子計算機體系結構方案，在該方案中，使用經典計算機完成量子程序中的常規數據處理和程序邏輯控制，而將量子計算部件做為協處理器，只負責完成量子計算。 -
By combining the system developing levels with the application environment, the redundancy level was positioned in the model - level redundancy, a / d connected in series with the master as the redundant unit, the bi - processor models drive on outer model
結合系統開發層次與使用環境，將冗餘級別定位於模塊級冗餘，提出了以a d與主機串聯形成的處理器模塊為冗餘單位、雙處理器模塊共同驅動一套外設的模型。 -
The receiver unit mainly consisted of the digital down converter, matched filter, integration and dump module, power detector, symbol tracking processor, differential demodulator, parallel - to - serial conversion module, output processor and afc module
接收部分主要有數字下變頻、數字匹配濾波器、積分清洗、功率檢測、符號跟蹤處理、差分解調、並串處理、自動頻率跟蹤處理等模塊。 -
Using the high - performance digital signal processor ( dsp ) as cpu, the author designs the medium - speed sampling and processing unit of the fault locator. on the one hand, this unit can sample voltages and currents of the line synchronously ; on the other hand, this unit can start the fault locator up and select the fault lines when faults occur
本文作者還以高性能的數字信號處理器（ dsp ）為cpu設計了測距裝置的中速采樣處理單元，該處理單元一方面可以實現線路電流電壓信號的同步數據採集，另一方面可以完成測距裝置的故障啟動和故障選線任務。 -
Each demonstration unit, or " dragon head ", will consist of a processor, feedlots and households, which established vertical contractual relationships for the production and marketing of cattle
每個示範單位或「頭」單位都將包括加工廠飼養場和農戶，他們為牛的生產和市場營銷建立了垂直的合同關系。 -
Then, the work researches multithread processor architecture based on the armp. this dissertation focused on the branch predictor of high performance processor and fetch unit of selective execution of multithread architecture
接著，本文以armp為基礎深入了解國內外目前最先進的多線程處理器系統結構研究工作，明確了該領域研究的發展方向和研究難點。 -
Then, chapter four describes the details of the implementation of video processing subsystem from processor unit, storage architecture unit, data i / o host - slave bus, data i / o interconnection unit four design aspects. in chapter five, host application programs and windows device driver design based on wdm are discussed
第四章從處理器單元設計、存儲結構單元設計、數據i o主從總線設計，數據i o互連總線設計和系統控制中心單元設計五個方面分析視頻處理子系統的詳細設計。
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