verification methodology 中文意思是什麼

verification methodology 解釋
核實方法學
  • verification : n. 1. 證實，證明，確定；核驗，驗證，核對；檢驗，校驗。2. 【法律】訴狀[答辯書]結尾的舉證說明。
  • methodology : n. 方法學，方法論；研究法；【生物學】分類法。adj. -logical
  1. This dissertation studies the reuse methodology in the verification, analyzes the intellectual property standalone verification platform, discusses the design methods of bus function model and bus monitor in the reusable function verification platform, investigate the difference in the reusability of the implementation mode of task - based and state machine - based bus function model and present the reusability design rules in the bus monitor

    在此基礎上，分析了ip單獨驗證平臺，並討論了該驗證平臺中總線功能模型和總線監視器的設計方法，研究了基於任務和基於狀態機兩種總線功能模型的實現方式在可重用性方面的區別，並提出了總線監視器的可重用性設計規則。
  2. This paper introduces a new methodology that uses - it knowledge structures, a specific form of kripke semantics for epistemic logic, to analyze communication protocols over hostile networks. the paper particularly focuses on automatic verification of authentication protocols. our approach is based on the actual definitions of a protocol, not on some difficult - to - establish justifications

    認知邏輯的kripke語義已經被成功應用到通信協議的推理分析中例如，交替位協議alternating bit protocol的分析，及最近的對tcp的分析.因為信息交換本質上可以看成是個認知過程，用認知邏輯可以很方便地表達
  3. Research methodology includes verification of historical article review, field visit and dictation interview

    主要研究方法包括史料文獻查證，實地訪查，口述訪談。
  4. The proposed methodology is different from many previous approaches to automatic verification of security protocols in that it is justification - oriented instead of falsification - oriented, i. e., finding bugs in a protocol

    由burrows ， abadi和needham提出的ban邏輯及類ban邏輯曾在應用認知邏輯驗證安全協議上作出了嘗試
  5. This dissertation is supported by the following projects : national foundation for science research on the theory of sub - deep micro and super high speed multimedia chip design " ( no. 6987601 0 ) national foundation for high technology research & development " interface of vlsi ip core and related design technology " ( 863 - soc - y - 3 - 1 ) a - national r & d programs for key technologies for the 9th five - year plan research on high level language description and embedded technology for mcu " ( 97 - 758 - 01 - 53 - 08 ) national foundation for the ministry of education, prc " research on the optimal theory and methodology of soc software / hardware integration co - design and co - verification " ( moe [ 2001 ] 215 ) national foundation for science and technology publication " design of interface circuit for computer with verilog " [ ( 99 ) - f - l - 011 ] a deep research on system level design methodology of 1c and the design technology of mcu - ip and interface ip are made in this dissertation. the main work and achievements are as follows : 1 building block principle and the building block component maximum principle are brought forward based on the research of developing history of ic design

    本文基於以下科研項目撰寫：國家自然科學基金「深亞微米超高速多媒體晶元設計理論的研究」 （ 69876010 ）國家863計劃「超大規模集成電路ip核介面及相關設計技術」 （ 863 - soc - y - 3 - 1 ）國家「九五」重點科技攻關「 mcu高層語言描述及其嵌入技術研究」 （ 97 - 758 - 01 - 53 - 08 ）國家教育部「 soc軟硬體集成協同設計和驗證優化理論和方法研究」 （教技司[ 2001 ] 215 ）國家科技學術著作出版基金「 verilog與pc機介面電路設計」 （ 99 - f - 1 - 011 ）論文的主要工作和取得的成果如下： 1 、在研究集成電路設計方法學發展歷史的基礎上，提出了設計的積木化原則和積木元件最大化原則。
  6. In methodology, it adopts the ways which are generally taken in the field of sociology of combining empirical positive investigation with theoretical logical verification, of combining macroscopic analysis with microscopic observation

    文章最後指出需因勢利導，努力化消極因素為積極因素。文章在方法論上採取了社會學通常做法即經驗的實證調查研究與邏輯的理論證明相結合、宏觀分析和微觀考察相結合。
  7. These methods are motivated by advanced pattern recognition and computer vision methodology, and have achieved promising results in writer recognition and verification experiments

    這些方法吸收了模式識別和計算機視覺領域的最新理論和技術，在書寫人識別和驗證實驗中取得了很好的效果。
  8. A transaction - based verification methodology ( tbv ) can be the most effective method to make functional verification

    大量實踐證明，基於事務的驗證重用方法學是提高功能驗證效率的最有效的方法之一。
  9. Similar with design verification problem, to predigest chip level layout synthesis problem, the layout synthesis based on the standard - cell methodology can be divided into two levels : inner standard - cell and among standard - cells. however, along with the increasing of chip size, chip level layout synthesis problem become more complex if it still bases on general manual standard - cell. because the router cannot impose the characteristic of the transistors in the standard - cell, it may reduce the performance of the whole chip

    通常，基於標準單元布圖模式將版圖綜合劃分成單元內與單元間兩個層次，以簡化晶元級自動版圖綜合問題的復雜性；但隨著晶元規模的不斷擴大，基於主要以手工定製的小規模標準單元，晶元級版圖綜合問題的復雜性不斷增大，且標準單元間布線無法充分利用單元內晶體管特徵，影響晶元的整體性能。
  10. Design verification problem needs hierarchy methodology. because the effect of interconnection has taken in the highest flight, design verification for the interconnection network, for example, only the completed verification for performance of power supply of p / g network can ensure the reliability of chip

    由於晶元內互連線作用已佔相當重要的地位，在對互連線網路作精確的設計驗證，例如，晶元電源地網的供電性能的驗證，是晶元工作的可靠性的保證。
  11. Safety of machinery - reduction of risks to health from hazardous substances emitted by machinery - methodology leading to verification procedures

    機械的安全性.減少機械產生的危險物質對健康造成危害.驗證程序的指導方法
  12. Safety of machinery. reduction of risk to health from hazardous substances emitted by machinery. part 2 : methodology leading to verification procedures

    機器安全性.降低機器中產生的有害物質對健康的危害.第2部分:檢驗程序制定方法
  13. Safety of machinery - reduction of risks to health from hazardous substances emitted by machinery - part 2 : methodology leading to verification procedures

    機械安全性.減少機械散發有害物質對健康影響的危險性.第2部分:得出驗證程序的方法
  14. Safety of machinery - reduction of risk to health from hazardous substances emitted by machinery - part 2 : methodology leading to verification procedures ; german version en 626 - 2 : 1996

    機械安全性.減少機器排放有害物質對健康的危害.第2部
分享友人
分享到 Line

分享到臉書