video channel output 中文意思是什麼
video channel output
解釋
視頻通道輸出-
Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo
本文首先對數字減影血管造影（ dsa ）成像系統的組成結構和數據流向進行了深入研究和分析，並對系統中的數據流向進行了完整的歸納和總結，給出了x線數字成像系統中的高速大容量數據通道的設計方案；在對sdram的控制方式做了深入探討后，給出了實現大容量多條sdram共同工作的解決方案，在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲；通過對pci總線介面的深入研究，優化後端狀態機設計和低層驅動程序開發，給出了完整的pci介面方案實現高速dma數據傳輸，完全可以滿足視頻傳輸要求；深入研究了基於大規模可編程器件的數字系統設計方法，針對通用fifo使能信號漂移、輸出數據難于建立和保持等設計難點，提出了利用fpga中的鎖相環提供多個時鐘相移的信號來提高系統穩定性的解決方案，從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。 -
In improved uep scheme, the syntax elements belonged to luminance parts and chrominance parts was reassigned to different data partitions. those packets containing syntax elements belonged to luminance parts were got error protection at high level so as to guarantee their correctness during transmitting in error - prone network. simulation has shown that using proposed scheme, the packing tradeoff is decreased 8240 bytes in error - free channel and also the output bits and bit rate of coded video stream are decreased 2. 70kbits and 0. 33 kbps respectively
模擬實驗表明，本方案能在無噪通道中有效降低編碼器端8240位元組的打包開銷和2 . 70kbit的輸出比特數以及0 . 33kbps的比特率，而在有噪通道中可使解碼輸出重構視頻圖像的視覺質量得到一定程度的提高，亮度分量峰值信噪比可增加近1db 。 -
The video signal processing circuit realizes the primary catching, filtering and signal amplifying. variable threshold binarization processing circuit and two - channel counter are designed to sample to count the output pulse signal, which is processed, deposited and displayed in microprocessor. the communication interface circuit with the computer is also designed
視頻信號處理電路完成了原始信號的初級捕捉、濾波、視頻放大等處理，設計了浮動閾值二值化處理電路，採用兩路計數器對輸出脈沖信號采樣計數，最後送入微處理器進行運算處理，可實現測量值的儲存、顯示等，並設計了與上位機的通訊介面。 -
The input video is sampled at the transmitter of the sub - system, and code stream is sent to channel after compression. at the receiver, output video is reconstructed after decompression
在發送端對輸入的視頻信號進行數字採集、壓縮，壓縮后的數據流經通道傳輸至接收端解壓縮，輸出顯示。 -
The algorithm study is in detail that one channel of video - stream is recompressed by mpeg - 2 standard so that its bit - rate will be changed lower. then, multi - date streams will be processed by the technology of statistical remultiplex. the dynamic signals of every single data - stream " output can drive the values of bit - rate of the corresponding single data - stream
本次演算法研究具體地說就是按照mpeg - 2的標準對單路mpeg - 2視頻流再次壓縮，將其碼率變的更低，並且提出對多路碼流進行統計復用，根據單路碼流的輸出動態信息對碼流進行動態的調整的框架。
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