亞閾的 的英文怎麼說

中文拼音 [yǎyùde]
亞閾的 英文
subthreshold
  • 閾 : 名詞1. [書面語] （門坎兒） threshold; doorsill2. （界限; 范圍） threshold
  • 的 : 4次方是 The fourth power of 2 is direction
  1. Due to the image exists the instances of spin and distortion, in order adopting part small template proceed matching in order to reduce thereof impacts by as possible, besides small template matching may decrease calculation quantity, and it is propitious to real time of matching. looking into be on the impact of illumination, chromatism, under cloak circumstance template size and quantity select versus matching rate. matching primitive chooses gray, gray information measure large and most easy to obtain, but it is rather effected by illumination condition and chromatism, maximum matching rate restricted to 70 %

    瓷磚缺陷檢測採用待測圖像與標準圖像作差法，作差法對匹配精度要求較高，因此在匹配誤差存在的點進一步做了亞像素級的匹配;導彈目標識別，採用背景匹配的方法，統計背景移動距離指導目標的識別;叢林中移動目標識別，採用作差法找到目標區和背景區，分別採用不同的模板和閾值匹配，統計目標區匹配結果。
  2. The study shows that the impact of incomplete ionization on sic mosfet is more notable in subthreshold region than in strong inversion region

    對于sicmosfet ，雜質不完全離化的影響主要在亞閾區。
  3. The results of the analysis show that the impact of incomplete ionization on sic mosfet is more notable in subthreshold region than in strong inversion region

    分析結果表明不完全離化對sicmosfet的影響主要集中在亞閾區。
  4. Under self - heating stress, a general degradation in subthreshold characteristic was observed, which is the consequence of defect generation along overall channel

    這主要是由於在自加熱應力下，整個溝道中都出現了缺陷態的產生，從而使器件的亞閾值擺幅發生了退化。
  5. Standard test method for separating an ionizing radiation - induced mosfet threshold voltage shift into components due to oxide trapped holes and interface states using the subthreshold current - voltage characteristics

    利用亞閾值安伏特性測定由於氧化空穴和界面態產生的電離輻射感應金屬氧化物半導體場效應晶體管閾電壓偏移分量的標準試驗方法
  6. A model of the interface state density distribution near by valence band is presented, and the dependence of the threshold voltage on temperature, the c - v characteristics and the subthreshold characteristics are predicted exactly with this model ; the effects of s / d series resistance on the output characteristics, transfer characteristics and effective mobility of sic pmosfets are analyzed. thirdly, the output characteristics and the drain breakdown characteristics are modeled with the procedure medici. the output characteristics in the room temperature and 300 ? are simulated, and the effects of gate voltage. contact resistance, interface state and other factors on sic pmos drain breakdown characteristics are analyzed

    提出了一個價帶附近的界面態分佈模型，用該模型較好地描述了sicpmos器件閾值電壓隨溫度的變化關系、 c - v特性曲線以及亞閾特性曲線；分析了源漏寄生電阻對sicpmos器件輸出特性、轉移特性以及有效遷移率的影響；論文中用模擬軟體medici模擬了sicpmos器件的輸出特性和漏擊穿特性，分別模擬了室溫下和300時sicpmos器件的輸出特性，分析了柵電壓、接觸電阻、界面態以及其他因素對sicpmos擊穿特性的影響。
  7. Based on the hydrodynamic energy transport model, the influence of variation of negative junction depth caused by concave depth on the characteristics of deep - sub - micron pmosfet has been studied. the results are explained by the interior physical mechanism and compared with that caused by the source / drain depth. research results indicate that with the increase of negative junction depth ( due to the increase of groove depth ), the threshold voltage increases, the sub - threshold characteristics and the drain current driving capability degrade, and the hot carrier immunity becomes better in deep - sub - micron pmosfet. the short - channel - effect suppression and hot - carrier - effect immunity are better, while the degradation of drain current driving ability is smaller than those with the increase of depth of negative junction caused by source / drain junction shallow. so the variation of concave depth is of great advantage to improve the characteristics of grooved - gate mosfet

    基於能量輸運模型對由凹槽深度改變引起的負結深的變化對深亞微米槽柵pmosfet性能的影響進行了分析，對所得結果從器件內部物理機制上進行了討論，最後與由漏源結深變化導致的負結深的改變對器件特性的影響進行了對比.研究結果表明隨著負結深（凹槽深度）的增大，槽柵器件的閾值電壓升高，亞閾斜率退化，漏極驅動能力減弱，器件短溝道效應的抑制更為有效，抗熱載流子性能的提高較大，且器件的漏極驅動能力的退化要比改變結深小.因此，改變槽深加大負結深更有利於器件性能的提高
  8. After introduction of the tranlinear loop principal, the bjt current controlled conveyor has been designed by using mixed tranlinear loop voltage follower. as for modern integrated circuit, the model of mos transistor, the active resistance and the current mirror integrated circuit formed by mos transistor are introduced. the cmos current controlled conveyor has been derived from mixed tranlinear loop cmos voltage follower based on weak inversion operation

    針對現代集成電路的工藝，本文對mos晶體管的工作原理進行了簡要的敘述，討論了有源電阻和電流鏡的實現方法，並利用mos晶體管的亞閾值特性組成混合跨導線性迴路完成對應的電壓跟隨器的設計，推導出了基於cmos技術的電流控制傳送器。
  9. These figures have not been recommended for the whole of asia but nevertheless, do provide an alternative scale to the global figures which may not fully take into account the differences in fat distribution and body composition between caucasian and asians

    。雖然這兩個閾值還未向全亞洲推薦使用，但是這兩個閾值的確可以代替那些全球通用的閾值，後者未完全考慮高加索人和亞洲人脂肪分佈和體成分差異。
  10. More recently, lower thresholds for waist circumference have been recommended for asian populations

    最近，對亞洲人群推薦了一個更低的腰圍閾值。
  11. The character of threshold voltage in vlsi circuit is analyzed. it can make a serious effect on power dissipation and performance. an algorithm based on partition is designed to choose the most favorable working voltage and threshold

    在低電壓電路中，既要使電路實現正常的開關，又必須限制延時和亞閾值漏電流的急劇增加，就必須認真地選擇工作電壓和閾值電壓。
  12. The algorithms employed in this paper are redesigned or improved for grid images. for example, an adaptable moving window gray scale threshold image segmentation method is proposed originally, a parallel template matching thinning algorithm is improved greatly, a sub - pixel image processing algorithm based on b - spline interpolation is present independently. 3

    其中獨立設計了自適應的移動窗口灰度閾值圖象分割法，優化設計了并行模板匹配細化演算法，獨立提出了基於三次均勻b樣條插值放大局部圖象的亞象素圖象處理演算法，並都取得了較好的處理效果。
  13. The dominance and properties of the cmos integrated reference were also described, and the research meaning was pointed out. related device theory and process model used in design were described. the temperature related model and the influencing factor of two active devices, subthreshold mosfet and pnp substrate transistor, based on cmos process were analyzed and compared, and pointed out that the pnp substrate transistor was more fit for being the temperature compensating device for bandgap reference

    闡述了設計中相關的器件理論與工藝模型，對cmos工藝下的兩種有源器件，即亞閾值工作狀態下的金屬場效應晶體管（ mosfet ）及襯底pnp雙極型晶體管（ bjt ）的溫度模型及其影響因素進行了分析和比較，指明襯底pnp雙極型晶體管更適合作為基準源的溫度補償元件。
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