指令級并行 的英文怎麼說
中文拼音 [zhǐlìngjíbīngháng]
指令級并行
英文
ilp-
Based on these two factors mentioned above and the difficulty to implement in c compiler, this paper proposed a method of modifying operand type by inserting instruction lw or sw at assemble level as well as instruction scheduling. therefore, this can generate effective parallel instructions and correspondingly improve the performance and density of object code
本文在分析了上述兩個限制并行指令生成的主要因素以及很難在編譯器中實現并行指令生成的基礎上，提出了在匯編級檢查指令的操作數類型，通過插入lw或sw指令來改變操作數類型及指令調度的方法，能夠有效的生成并行指令，提高了代碼運行效率和代碼密度。Adaptive stack cache with fast address generation policy decouples stack references from other data references, improves instruction - level parallelism, reduces data cache pollution, and decreases data cache miss ratio. stack access latency can be reduced by using fast address generation scheme proposed here
該方案將棧訪問從數據高速緩存的訪問中分離出來，充分利用棧空間數據訪問的特點，提高指令級并行度，減少數據高速緩存污染，降低數據高速緩存失效率，並採用快速地址計算策略，減少棧訪問的命中時間。Software pipelining ( swp ) is an effective technique for loop optimization
軟體流水是開發循環指令級并行的重要編譯技術。( 4 ) we make further improvement in fox algorithm on processors organized as a rectangular grid, and we also develop multi - level parallelisms and make performance optimization for this improved algorithm on smp cluster at process level, thread level and instruction level
（ 4 ）對長方網格上的并行矩陣乘演算法做了進一步改進，並針對改進演算法，分別從進程級、線程級和指令級對其進行多級并行性開發與性能優化。Software pipelining is a loop scheduling technique that extracts ilp by overlapping the execution of several consecutive iterations
軟體流水是開發循環程序指令級并行性的重要編譯優化技術。This thesis mainly focuses on the multi - level parallelism development and performance optimization of scientific programs on this architecture, and our works are summarized as follows. ( 1 ) we put forward the multi - level parallel computing time model, which is suitable for smp cluster to analyze program performance from the micro - aspect. we also provide a multi - level parallel optimization speedup model based on the single - processor speedup factor, which can evaluate program performance from three parallel levels and guide us to improve the programs
本文圍繞這種多級并行體系結構中的超節點級、節點級和單機指令級三個層次的并行性開發與優化，在科學計算程序的綜合優化技術研究方面做了以下的工作與創新: （ 1 ）針對smp集群體系結構提出了多級并行計算時間模型，用於程序性能的微觀分析;將單機處理速度與加速比統一起來，提出了基於單機優化加速因子的多級并行優化加速比評價模型，該模型分別從三個并行層次的角度出發對程序性能進行評價，並指導對程序的改進與優化。Based on the dlx simulator, smarcof is modified with sma specific extension and heuristic optimizing rules. simulation of spec code shows that above rules could exploit hybrid parallelism effectively with rather low overhead
基於spec代碼的模擬表明該方式能夠有效的挖掘系統的潛力，實現深度的指令級并行和線程級并行開發。Multithreaded microprocessor, which has many hardware contexts sharing an execution core, can efficiently exploit both the instruction level parallelism and thread level parallelism to acquire higher performance and better performance / power ratio
多份硬體現場共享一組執行單元的多線程處理器能靈活地利用程序中的指令級并行和線程級并行，從而提供更好的性能。3 ) the instruction - level parallel calculation of streamlines on 3d curvilinear grids has been implemented firstly by using the streaming simd extensions ( sse ), which are a set of extensions of the intel pentium hi / 4 processor. compared with the conventional algorithm, sse - based algorithm coded by vector class library enhances performance about 55 %, and coded by inlined - assembly is about 75 %
） pentium （ pentium4 ）處理器的流simd擴展（ sse ） ，首次實現了3d曲線網格流線計算的指令級并行，與傳統演算法相比，向量類庫編碼實現的sse演算法將性能提高了55左右，嵌入匯編實現提高了75左右。Epic defines a new style of architecture that enables higher levels of instruction level parallelism ( ilp ) without unacceptable hardware complexity
Epic是一種顯性并行指令計算體系結構，主要思想是利用編譯器和處理器的協同能力來提高指令級并行度。Firstly, to improve the mpiformatdb ’ s speed, a novel parallel algorithm based on shared memory architecture is presented. by adding openmp directives, the cycled parallel structure is formed from the serial algorithm
為了提高mpiformatdb的性能，本文提出一種基於共享存儲結構的并行演算法，通過在原串列演算法中增加openmp編譯指導命令來構造循環級并行結構。Nowadays, all sorts of multimedia services and network services develop flourishingly. it is far from enough to meet the performance requirement of such services to exploit ilp only
在各種多媒體服務以及網路服務蓬勃發展的今天，僅僅開發傳統的指令級并行性已經遠遠不能滿足這些服務對微處理器的性能要求。State - of - the - art microprocessors exploit instruction level parallelism ( ilp ) to achieve high performance on applications by searching for independent instructions in a dynamic window of instructions and executing them on a wide - issue pipeline
對于當前軟體中佔主要部分的串列程序而言，微處理器主要依靠開發程序的指令級并行（ ilp ）來提高性能。One of the key elements to achieving higher performance in microprocessors is executing more instructions per cycle. however, dependencies among instructions, varying latencies of certain instructions, and execution resources constraints, limit this parallelism considerably. in order to exploit instruction level parallelism, processor should employ data dependence analysis to identify independent instructions that can execute in parallel
當前，在微處理器體系結構研究中，為了充分提高微處理器的處理性能，主要採用了指令級并行技術（ ilp ） ，指令級并行性的開發程度對發揮微處理器的硬體特性，提高程序運行性能至為關鍵。分享友人