指令級 的英文怎麼說
中文拼音 [zhǐlìngjí]
指令級
英文
order-
Firstly, the thesis summarizes the compilation optimizations in modern compiler and the direction of low - power compilation, then analyses the modern compiler such as impact and trimaran, especially their register allocation strategies
本文首先概述了現代編譯器中的編譯優化技術以及低功耗編譯的方向，具體分析了面向指令級優化的編譯器impact和trimaran ，分析了其中的組成模塊，並深入了解其中的寄存器分配機制。In this paper, an embedded 16 - bit processor core is designed, based on the characteristics of the wireless communication algorithm and instruction level acceleration technology
文章結合無線通信處理演算法的特點，利用指令級加速技術，設計了一種基於無線通信中復數運算的16位嵌入式處理器核。Adaptive stack cache with fast address generation policy decouples stack references from other data references, improves instruction - level parallelism, reduces data cache pollution, and decreases data cache miss ratio. stack access latency can be reduced by using fast address generation scheme proposed here
該方案將棧訪問從數據高速緩存的訪問中分離出來，充分利用棧空間數據訪問的特點，提高指令級并行度，減少數據高速緩存污染，降低數據高速緩存失效率，並採用快速地址計算策略，減少棧訪問的命中時間。After detailed analysis of microprocessor at89c51, we fixed a data path oriented scheme to test at89c51 and in this paper we have given the test program generation procedure according to most data paths of at89c51
At89c51的指令級測試以匯編測試程序作為測試激勵，實驗中通過對at89c51的詳細分析，確定了針對通路的測試策略，並給出了測試程序產生方法。The experimental results indicate that it is feasible to applied at - speed current testing to at89c51 microprocessor at instruction level. through testing of data paths, we can not only detect the faults arose by data path, but also find the faults brought in by control parts
實驗結果表明，用全速電流測試在指令級對at89c51微處理器進行測試是可行的，通過測試所有的數據通路，不僅可以檢測數據通路的故障，而且可以檢測由於控制錯誤而引起的數據傳送錯誤。Software pipelining ( swp ) is an effective technique for loop optimization
軟體流水是開發循環指令級并行的重要編譯技術。Therefore, in order to ensure system real time needs and decrease software power consumption of wearable computing system, this thesis proceed the research from two parts : one is seeking low power consumption design to achieve efficient running via choosing and applying instructions ; the other is adopting the proceeding optimization attemperment to realize efficient and low power consumption software attemperment
在基本保證系統實時需求，並有效地減小可穿戴計算系統的軟體能耗的目標前提下，本文嘗試從指令和程序設計上進行低功耗設計方法的研究。針對指令級別，本文希望藉助指令的低功耗選用與執行，實現高效運算的低功耗設計。針對程序設計，本文嘗試採用進程優化調度的方式，實現可穿戴計算系統低功耗且高效的軟體調度。( 4 ) we make further improvement in fox algorithm on processors organized as a rectangular grid, and we also develop multi - level parallelisms and make performance optimization for this improved algorithm on smp cluster at process level, thread level and instruction level
（ 4 ）對長方網格上的并行矩陣乘演算法做了進一步改進，並針對改進演算法，分別從進程級、線程級和指令級對其進行多級并行性開發與性能優化。Software pipelining is a loop scheduling technique that extracts ilp by overlapping the execution of several consecutive iterations
軟體流水是開發循環程序指令級并行性的重要編譯優化技術。This thesis mainly focuses on the multi - level parallelism development and performance optimization of scientific programs on this architecture, and our works are summarized as follows. ( 1 ) we put forward the multi - level parallel computing time model, which is suitable for smp cluster to analyze program performance from the micro - aspect. we also provide a multi - level parallel optimization speedup model based on the single - processor speedup factor, which can evaluate program performance from three parallel levels and guide us to improve the programs
本文圍繞這種多級并行體系結構中的超節點級、節點級和單機指令級三個層次的并行性開發與優化，在科學計算程序的綜合優化技術研究方面做了以下的工作與創新: （ 1 ）針對smp集群體系結構提出了多級并行計算時間模型，用於程序性能的微觀分析;將單機處理速度與加速比統一起來，提出了基於單機優化加速因子的多級并行優化加速比評價模型，該模型分別從三個并行層次的角度出發對程序性能進行評價，並指導對程序的改進與優化。Based on the dlx simulator, smarcof is modified with sma specific extension and heuristic optimizing rules. simulation of spec code shows that above rules could exploit hybrid parallelism effectively with rather low overhead
基於spec代碼的模擬表明該方式能夠有效的挖掘系統的潛力，實現深度的指令級并行和線程級并行開發。Multithreaded microprocessor, which has many hardware contexts sharing an execution core, can efficiently exploit both the instruction level parallelism and thread level parallelism to acquire higher performance and better performance / power ratio
多份硬體現場共享一組執行單元的多線程處理器能靈活地利用程序中的指令級并行和線程級并行，從而提供更好的性能。3 ) the instruction - level parallel calculation of streamlines on 3d curvilinear grids has been implemented firstly by using the streaming simd extensions ( sse ), which are a set of extensions of the intel pentium hi / 4 processor. compared with the conventional algorithm, sse - based algorithm coded by vector class library enhances performance about 55 %, and coded by inlined - assembly is about 75 %
） pentium （ pentium4 ）處理器的流simd擴展（ sse ） ，首次實現了3d曲線網格流線計算的指令級并行，與傳統演算法相比，向量類庫編碼實現的sse演算法將性能提高了55左右，嵌入匯編實現提高了75左右。Ilp instruction level parallelism
指令級平行運算Epic defines a new style of architecture that enables higher levels of instruction level parallelism ( ilp ) without unacceptable hardware complexity
Epic是一種顯性并行指令計算體系結構，主要思想是利用編譯器和處理器的協同能力來提高指令級并行度。On the software side, compiler inserts prefetch instructions explicitly ; on the hardware side, an sma cache filter is added to cut down unnecessary prefetch. 4 guided by feedback - based optimization strategy, the paper presents a dynamic profile based continuous optimization framework - smarcof
4研究了基於動態輪廓信息的軟硬體聯合持續優化機制，並在dlx模擬器的基礎上設計並實現了一個完整的指令級模擬平臺和基於上述優化規則的編譯框架smarcof 。Instruction level language
指令級語言In this paper we have proposed instruction level at - speed current testing method taking both the characteristics of microprocessor and at - speed current testing into account
本文針對微處理器的特點，提出了指令級全速電流測試方法。In chapters optimization methods is depicted in detail on tm1300 and some optimization methods are introduced. and in chapter6 i will introduce the system implement and its performance
第五章將重點介紹基於tm1300的優化方法，對運動估計， dct和量化的演算法優化以及指令級的優化進行了介紹。Nowadays, all sorts of multimedia services and network services develop flourishingly. it is far from enough to meet the performance requirement of such services to exploit ilp only
在各種多媒體服務以及網路服務蓬勃發展的今天，僅僅開發傳統的指令級并行性已經遠遠不能滿足這些服務對微處理器的性能要求。分享友人