指令緩存 的英文怎麼說

中文拼音 [zhǐlìnghuǎncún]
指令緩存 英文
instructions cache
  • 指 : 指構詞成分。
  • 緩 : Ⅰ形容詞1 （遲; 慢） slow; unhurried 2 （緩和; 不緊張） not tense; relaxed Ⅱ動詞1 （延緩; 推遲） d...
  • 存 : 動詞1 （存在; 生存） exist; live; survive 2 （儲存; 保存） store; keep 3 （蓄積; 聚集） accumulat...
  • 指令 : 1 （指示; 命令） instruct; order; direct2 （上級機關對下級機關的指示） instructions; order; direc...
  • 緩存 : buffer
  1. This directive configures the page to be cached. the

    此指令配置頁面以進行緩存。
  2. Itc instruction trace cache

    指令追蹤緩存
  3. Directive to set your page s cacheability, you must declare the

    指令設置頁的可緩存性，則必須聲明
  4. User controls can support caching directives that are separate from the host page

    用戶控制項支持獨立於宿主頁的緩存指令。
  5. The paper elaborates risc technology characteristic and 5 - stage pipeline architecture and function of the 64 - bit risc cpu, and dwells on 64 - bit vega cpu characteristic, and details the eda technology and the main flow of asic design, and elaborates the operation and exception process of the vega cpu and virtual instruction address " architecture and generation, and details cache architecture and mmu. the master dissertation dwells on virtual address translating into physical address, instruction cache finding address and instruction fetching, too

    詳細的闡述了64位vegacpu的特點，闡述了eda技術和asic設計的主要流程，闡述了vegacpu流水線結構、流水線操作、流水線暫停和異常處理，虛擬指令地址的結構和產生， mmu結構，包括指令tlb結構和虛擬指令地址向物理指令地址的生成流程， cache結構，尋址原理和指令的寫策略，指令高速緩存的尋址原理和結構，以及指令的獲取流程。
  6. Cache control directive and the no - cache

    緩存控制指令和no - cache
  7. In the http caching protocol, this is achieved using the no - cache cache control directive

    在http緩存協議中，這是通過no - cache緩存控制指令實現的。
  8. In the http caching protocol, this is achieved using the no - store cache control directive

    在http緩存協議中，這是使用no - store緩存控制指令實現的。
  9. Table 9. cache management instructions

    表9 .高速緩存管理指令
  10. The powerpc architecture contains cache management instructions for both application - level cache accesses

    Powerpc體系結構包含了面向應用級高速緩存訪問的高速緩存管理指令。
  11. Adaptive stack cache with fast address generation policy decouples stack references from other data references, improves instruction - level parallelism, reduces data cache pollution, and decreases data cache miss ratio. stack access latency can be reduced by using fast address generation scheme proposed here

    該方案將棧訪問從數據高速緩存的訪問中分離出來，充分利用棧空間數據訪問的特點，提高指令級并行度，減少數據高速緩存污染，降低數據高速緩存失效率，並採用快速地址計算策略，減少棧訪問的命中時間。
  12. Before the connectting between moden and other equipments, it works at the cammand mode, the cammand that is send to moden is used to set or manipulate the mode, after the connectting between moden and other equipments, it works at connectting mode, at that time, the cammand send from the computer is send to another computer which will pass the moden and telephone line. the moden control cammand is called " at " cammand, all the control manipulation is realized by sending the ascii character to moden, after the moden received the " at " cammand, it firstly judges the cammand, secondly, it analyses and executes the cammand, finnally, it executes a response by sending back a ascii character, during the deseign of below - computer, we introduce in detail the deseign of system hardware and system software, below - computer system hardware and system software, below - computer is made up of microchip collecting and controlling system, which finish the strobe and water level data collection, display and disposal, deal with the communication with the above - computer, the microchip is the centre of data dealing with, the peripheral equipments are made up of data collecttion module, control cammand input module, display module, execute output module, and long - distance communication module

    在moden控制軟體的設計中，詳細敘述了moden正常工作時的幾個重要函數：初始化函數、撥號處理函數、應答處理函數、掛機處理函數，設計並調試了四個函數的通信程序，數據機工作時存在兩種模式，命令模式與連線模式，命令模式是針對功能設置的模式，連線模式是數據傳輸的模式。當數據機未與其他設備連接時，其處于命令模式，這時候下達給數據機的指令是作為數據機本身設置或操作用的；當數據機已經與其他設備連接時，其處于連線模式，所有在此時由計算機送至數據機的信息都將經由電話線傳送到另一部計算機上。專門使用於控制數據機的指令集被稱為「 at指令集」 ，對moden的所有操作（如撥號、應答、掛機等）都可以通過給moden發送ascii字元串來實現， moden在收到at命令后，先對命令進行判斷，接著分析和執行命令緩沖區中的命令，最後以自身的ascii字元對命令作出響應。
  13. Instruction to force the cache line containing the modified instruction to storage

    指令，強制包含有修改過的指令的高速緩存行進行存儲。
  14. By default mmus are implemented and they are constructed of 64 - entry hash based 1 - way direct - mpped data tlb and 64 - entry hash based 1 - way direct - mapped instruction tlb

    默認的存儲器管理單元實現由基於64個散列入口的單通道直接映射的數據后備式轉換緩沖區和基於64個散列入口的單通道直接映射的指令后備式轉換緩沖區組成。
  15. Two uart ports and one dsu port

    32kb指令緩存器及16kb數據緩存器
  16. If there is no instruction cache, this subroutine may be a no - op

    如果在你的目標機上，沒有指令緩存，則可能不做任何操作。
  17. On sparc and sparclite only, write this subroutine to flush the instruction cache, if any, on your target machine

    只在sparc和sparclite平臺上，這一功能調用用來刷新指令緩存。
  18. On target machines that have instruction caches, gdb requires this function to make certain that the state of your program is stable

    在有指令緩存的目標機上， gdb需要這一函數，以確定你的程序的狀態是穩定的。
  19. Caching pages, using either a page directive to have the entire page output cached, regardless of browser type, individual parameters, or data

    緩存頁，使用頁指令緩存整個頁輸出，而不管瀏覽器類型、各個參數或數據。
  20. Ck510 employs some new instructions in order to enhance the ability of signal processing. as compared with m - core, ck510 basically changes the architecture and increases pipeline depth from 4 to 7

    為了提高性能， c - core採用了指令緩存和數據緩存，而且流水線由m - core的四級變成七級。
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