指令緩沖器 的英文怎麼說
中文拼音 [zhǐlìnghuǎnchōngqì]
指令緩沖器
英文
i truction buffer-
By default mmus are implemented and they are constructed of 64 - entry hash based 1 - way direct - mpped data tlb and 64 - entry hash based 1 - way direct - mapped instruction tlb
默認的存儲器管理單元實現由基於64個散列入口的單通道直接映射的數據后備式轉換緩沖區和基於64個散列入口的單通道直接映射的指令后備式轉換緩沖區組成。A processor architecture is disclosed including a fetcher, packet unit and branch target buffer
母案摘要:揭露一種包含指令取器、封裝單元及分支目標緩沖器的處理器架構。In response to the branch target buffer detecting a taken branch that crosses multiple cache blocks, the fetch address is increased so that it points to the next cache block to be fetched but the search address is maintained the same
分支目標緩沖器會查出是否有預測會發生的分支指令跨過多個快取區塊,則讀取位址會指到下一個快取區塊而搜尋位址則會保持不變。In order to solve the problems about unfixed instruction length, stack - orientation and addressing virtualization in jvm instruction set, the instruction fetch unit, stack cache and mechanism of address translation in java chip system are studied
為了解決java虛擬機指令系統中指令不定長、面向堆棧和地址虛擬化等問題,本文研究了java晶元中取指部件、堆棧緩沖部件和地址轉換機制以及相應物理存儲器的管理等關鍵技術。The fetcher also generates a search address for output to the branch target buffer
指令讀取器亦產生搜尋位址輸出至分支目標緩沖器中。Auxiliary instruction buffer
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