振蕩模鎖定 的英文怎麼說
中文拼音 [zhèndàngmósuǒdìng]
振蕩模鎖定
英文
mode lock- 振 : 動詞1. (搖動; 揮動) shake; flap; wield 2. (奮起) brace up; rise with force and spirit
- 蕩 : Ⅰ動詞1 (搖動; 擺動) swing; sway; wave 2 (無事走來走去; 閑逛) loaf; wander; roam; loiter; go a...
- 模 : 模名詞1. (模子) mould; pattern; matrix 2. (姓氏) a surname
- 鎖 : Ⅰ名詞1 (安在開合處使人不能隨便打開的器具) lock 2 (姓氏) a surname Ⅱ動詞1 (上鎖) lock up 2 ...
- 定 : Ⅰ形容詞1 (平靜; 穩定) calm; stable 2 (已經確定的; 不改變的) fixed; settled; established Ⅱ動詞...
- 鎖定 : [電子學] lock; locking; [訊] lockout; [航海學] caging; locking in; lock in; latch down鎖定插銷 de...
-
In the thesis, some of the most important functional modules of the smart power control ics are researched and designed, including voltage reference, voltage regulator, under voltage lockout, oscillator and zero - voltage comparator. their topologies, schematics and layouts are introduced and developed
本畢業設計研究和提出了構成智能電源控制晶元的主要功能模塊,完成了其中若干模塊ip核的電路與版圖設計? ?包括基準電壓源,電壓調節器,欠壓鎖定比較器,振蕩器,電壓過零比較器等。The simulation results of the 2. 5 - d pic code for this new structure are presented. a 2. 5 gw peak output power with the frequency of l. 3ghz is generated with the input of 625kv voltage, dc input power of 18gw
然後對這種器件進行了數值模擬研究,得到的典型結果為:輸入電壓625kv ,輸入直流功率18gw ,輸出微波峰值功率為2 . sgw ,虛陰極振蕩頻率被鎖定,微波飽和時間小於sns ,頻率為1 . 3ghz 。Simulation results show 2. 5 gw output power with a frequency of 1. 25ghz can be generated with an input of 620kv voltage, dc input power of 10. 5gw electron beam. ( 3 ) the radial reflex klystron with an open foldaway - concentric cylindrical resonant cavity integrates the resonant cavity and reflex cavity within one foldaway coaxial cavity, so it is a very compact high power microwave device
然後對這種器件進行了數值模擬研究,得到的典型結果為:輸入電壓620kv ,輸入直流功率io . sgw ,輸出微波峰值功率為2 . sgw ,虛陰極振蕩頻率被鎖定,頻率為1 . 25ghz ,微波飽和時間小於sns 。But its performance is as same as common pll at a 5v voltage. so the pll performance is better than other plls at a 5v voltage, especially in power consumption and frequency. finally, the improved pll circuit used in the frequency synthesizer is composed of the improved vco, phase / frequency detector and charge pump. hspice simulation results show that the pll performance is better than other plls implemented by other vco in the same cmos technology
綜合以上的研究與設計,本文用所改進的壓控振蕩器、無死區鑒相器及電荷泵電路組成了用於頻率合成的鎖相環電路,並對此電路進行整體設計及模擬,結果表明其在鎖定時間、頻率范圍、輸出相位抖動及功耗方面具有較好的性能,且對提高鎖相環頻率合成器的整體性能有一定的作用。分享友人