故障覆蓋率 的英文怎麼說

中文拼音 [gùzhàngfùgělǜ]
故障覆蓋率 英文
fault coverage
  • 故 : Ⅰ名詞1 （事故） event; incident; happening; accident 2 （原因） cause; reason 3 （朋友; 友情） fr...
  • 障 : Ⅰ動詞（阻隔; 遮擋） block; hinder; obstruct Ⅱ名詞（遮擋物） barrier; block; obstacle
  • 覆 : 動詞1. [書面語] （蓋住） cover 2. [書面語] （底朝上翻過來; 歪倒） overturn; upset 3. 同 「復」 （Ⅱ1. 2. ）
  • 蓋 : 蓋名詞（姓氏） a surname
  • 率 : 率名詞（比值） rate; ratio; proportion
  • 故障 : hitch; breakdown; stoppage; fault; faulting; accident; blunder; bug; conk; failure; impairment; i...
  • 覆蓋率 : coverage factor
  • 覆蓋 : 1 （遮蓋） cover; overlap 2 （植被） plant cover; vegetation3 （保護層 覆蓋物） cover; covering; ...
  1. In this paper we investigate and carry out boundary scan ^ internal scan and built - in self - test three dft technologies in the embedded microprocessor estarl and get satisfying result, the fault coverage is more than 96 %

    本文針對嵌入式微處理器estar1的結構特點，研究並實現了邊界掃描、內部全掃描和內建自測試三種可測性設計技術，取得了良好的效果，故障覆蓋率達到96以上。
  2. Since the system parameters faulty coverage ratio and maintenance ratio influence the system ' s reliability and security, we analyze them and find out they play an important role in the evaluation of fault - tolerant system

    通過分析得出系統的故障覆蓋率與維修率在容錯系統的評價過程中起到非常重要的作用。
  3. These new methods adopt the circuit information contained in the power supply line current to realize the fault diagnosis. it can increase the fault coverage, reduce testing cost and improve the quality and reliability of ics

    它通過從電源電流信號中提取有效的信息來進行故障診斷，能夠提高故障覆蓋率，降低測試成本並提高集成電路產品的質量與可靠性。
  4. Using “ logical effort ” method to analyze the circuit ’ s critical path, and choose the optimized size of transistors in theory by this method. then, using sta technique simulates and analyzes the circuit to optimize transistors size further, and the circuit optimization arithmetic based on sta is gained. results proved that the optimization strategy of combining theory and practice have better effect

    結果證明，這種理論與實際結合的優化策略具有較好的效果;三、典型條件下，所實現版圖關鍵路徑延時1 . 38ns ，平均功耗45 . 3mw ，版圖面積0 . 05112mm2 ，達到了較小的延時、功耗和面積;四、針對所設計的算術邏輯部件，研究了一種獨特的內建自測試方法，只需較少的測試向量就可實現該部件100 %的故障覆蓋率，具有很高的效率和較低的代價。
  5. We investigated the architectures of three typical computer fault - tolerant systems such as triple modular admixture redundancy system, buildup dual computer comparing system and dual computer comparing system with hot standby, and descript them with the markov model. the reliability and safety model of these fault - tolerant systems are acquired through theoretical analyzing and calculating. with analyzing, we defined the systems " task interval available time section in reason, compared their reliability and safety and evaluated their reliabilities

    具體針對三模混合冗餘、增強型雙機比較及帶熱備份的雙機比較三種典型體系結構的計算機容錯系統進行了研究，統一用馬爾可夫模型進行描述，通過理論分析和計算，獲得各體系結構容錯系統的可靠度與安全度的數學模型；通過分析，合理定義了系統的任務工作期區間，並在此區間上比較分析了各體系結構容錯系統的可靠度與安全度情況，從而對各系統的可靠性指標進行了評價；根據上述三種系統的數學模型，在考慮系統故障覆蓋率與維修率兩個參數對系統可靠度與安全度影響的情況下，用matlab語言編制了計算機模擬程序。
  6. 1 murray b t, hayes j p. testing ics : getting to the core of the problem. ieee computer, nov. 1996, 29 : 32 - 39

    在絕大多數情況下，這就意味著如果我們運行偽隨機測試足夠長的時間，那麼我們就可以獲得100的故障覆蓋率。
  7. 3 zorian y. a distributed bist control scheme for complex vlsi devices. in proc. ieee vlsi test symposium vts 93, atlantic city, nj, 1993, pp. 4 - 9

    在混合bist方案中，我們會在偽隨機測試過程中終止偽隨機測試，因為剩下的偽隨機測試會降低偽隨機測試的故障覆蓋率。
  8. In this paper we use the bist in the testing of the ssrams in estarl according to the characteristics of the structure and get almost 100 % fault coverage

    本文針對estar1內部ssram的結構特點，實現了存儲器自測試，得到了將近100的故障覆蓋率。
  9. Experimental results have shown the efficiency of the algorithm to find near optimal solutions

    通過使用該特徵多項式，我們將獲得對待測電路的最大故障覆蓋率。
  10. Practical analysis and experimental results show that the naac detection optimal algorithm is characterized by almost full error coverage

    實踐表明， naac演算法生成的測試矩陣具有較高的故障覆蓋率。
  11. The transient power supply current ( iddt ) testing can detect some faults undetectable by any other test method, and increase fault coverage

    瞬態電流測試方法可以測試一些其他測試方法無法檢測的故障，進一步提高故障覆蓋率。
  12. Through the simulative experiments about iddq detecting bridge faults in cmos and bicmos circuits, the fault coverage of iddq can be estimated

    並對cmos電路與bicmos電路的橋接故障作了iddq檢測模擬實驗，分析了iddq檢測的故障覆蓋率。
  13. A sound dft not only has a high ratio of fault covering but also occupies little area of a chip in order to lower the usage of sources

    一個好的可測性設計不僅要具有較高的故障覆蓋率，而且測試模塊所佔晶元面積要做到盡量的小，以便少佔用資源。
  14. 8 chakrabarty k. test scheduling for core - based systems using mixed - integer linear programming. ieee trans. computer - aided design of integrated circuits and systems, oct. 2000, 19 : 1163 - 1174

    在我們的方案中，我們考慮了存儲器大小的約束多核系統的最小化測試時間以及較高的故障覆蓋率。
  15. Finally the design of rs decoder in this chip is described as an example of the hardware / software co - design based on asip, the construction and application of asip is also analyzed. the fourth chapter introduces the design flow using eda tools based on standard cell, then it presents the dft of this chip in detail which uses following techniques : full scan, bist and boundary scan to improve the fault coverage

    第四章，在對本晶元的基於標準單元eda設計流程進行了簡要說明基礎上，對本晶元採用的可測試性設計進行了詳細的分析和說明，本晶元中有機結合了多種可測試性設計技術：基於全掃描的方式、 bist測試技術、邊界掃描技術，保證了很高的測試故障覆蓋率。
  16. The dynamic power supply current ( iddt ) is a new window through which we can observe the switching activities in digital circuits. iddt testing methods make possible further increasing the fault coverage

    動態電流提供了一個觀測電路內部開關性能的新的窗口，動態電流測試方法為進一步提高故障覆蓋率提供了可能。
  17. Internal scan is advanced for the difficulty of fixing the state of sequential circuit, can be divided into full - scan and partial - scan. in this paper we use full - scan according to the real circumstance of estarl and get high fault coverage with very little impact on the circuit

    本文根據estar1的實際情況，設計實現了全掃描結構，既得到了較高的故障覆蓋率，又對電路的延遲和晶元面積影響很小（延遲時間增加0 . 3 ，晶元面積增加0 . 01 ） 。
  18. At present testing method based on current testing has become an important cmos digital integrated circuit testing method which has been accepted widely. in order to improve the fault coverage of the testing to meet the demands of people, the dynamic current ( iddt ) testing was proposed to detect some faults that cannot be detected by other testing methods in the middle 1990 ’ s

    90年代中期，人們提出了瞬態電流測試方法（ iddt ） ，以便發現一些其他測試方法所不能發現的故障，進一步從總體上提高測試的故障覆蓋率，滿足人們對高性能集成電路的需要。
  19. The conclusion is that by using ant algorithm, the fault coverage about near half standard circuits is best ; and the generation speed is very higher than strategate ' s

    與現有測試生成器相比，基於螞蟻演算法的測試矢量生成結果中，有近一半的標準電路獲得了最高的故障覆蓋率；在生成速度方面遠高於strategate等演算法。
  20. The experimental results illuminate the hierarchical test generation algorithm can greatly decrease the scale of test sets ( about 66 % ), but the fault coverage and time performance are lower than gate - level test generation

    實驗數據表明分層測試產生演算法能大大壓縮電路測試集（約為66 ） ，而故障覆蓋率有略微下降，時間性能也有些許降低。
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