數據幀時鐘 的英文怎麼說

中文拼音 [shǔjùzhèngshízhōng]
數據幀時鐘 英文
bfsr
  • 數 : 數副詞（屢次） frequently; repeatedly
  • 據 : 據Ⅰ動詞1 （占據） occupy; seize 2 （憑借; 依靠） rely on; depend on Ⅱ介詞（按照; 依據） according...
  • 幀 : 量詞（幅, 用於字畫）
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 數據 : data; record; information
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  1. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  2. Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo

    本文首先對數字減影血管造影（ dsa ）成像系統的組成結構和數據流向進行了深入研究和分析，並對系統中的數據流向進行了完整的歸納和總結，給出了x線數字成像系統中的高速大容量數據通道的設計方案；在對sdram的控制方式做了深入探討后，給出了實現大容量多條sdram共同工作的解決方案，在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲；通過對pci總線介面的深入研究，優化後端狀態機設計和低層驅動程序開發，給出了完整的pci介面方案實現高速dma數據傳輸，完全可以滿足視頻傳輸要求；深入研究了基於大規模可編程器件的數字系統設計方法，針對通用fifo使能信號漂移、輸出數據難于建立和保持等設計難點，提出了利用fpga中的鎖相環提供多個時鐘相移的信號來提高系統穩定性的解決方案，從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。
  3. In this method, data frames and characteristic of tms320c5402 chip are used

    提出了一種利用數據幀結合tms320c5402晶元特性進行時鐘同步維護的方法。
  4. In this thesis, the principle of polarized light wave transmit in optical fiber is researched, i. e. principle of ternary optical fiber communication is researched. based on the researches, the construction of ternary codes optical end machine and 3b2t optical end machine used in two - state fiber net are designed. the construction and component of circuits in 3b2t optical ( called sign converter circuit - scc ) are designed particularly, including : the clock synchronization module, the data synchronizing, code converting module, frame managing module and error exam and managing module

    本文研究了線偏光波動理論以及在光纖中的傳輸原理，研究了三值光通信系統原理和器件原理；在此基礎上，設計了三值光端機和在現有兩值光纖網中實現三值光通信的3b2t三值光端機的組成結構，詳細設計了3b2t三值光端機的電路組成部分（稱為電信號變換電路scc ） ，包括：時鐘同步模塊、數據同步模塊、碼元變換模塊、幀處理模塊及差錯檢測和處理模塊；而且在三值光纖通信基礎上，提出了四值光通信的原理和偏分復用的實用化方法。
  5. Four benchmark test sequences was used for the simulation, and the average number of cycles required to process a frame of the proposed architecture and average number of reference memory access required per frame has been computed

    本文用四個標準測試序列對所設計結構進行了模擬實驗，統計了該結構平均完成一次塊匹配的時鐘周期和平均處理一幀需對參考塊數據存儲器的訪問次數。
  6. In this paper, the method of in - bore abnormal phenomenon remote detecting is presented. considering of the multi - channel transient signals automatic acquisition, a project of pcm signal hardwire transmission data automatic acquire system is put forward. in this system, a pcm demodulate board is designed, it can decode the pcm code string which contain the information of the multi - channel transient signals, it also can catch the useful data automatically, and transmit these data to upper pc by rs485

    在該系統中，為了能夠解調出包含多路動態信號數據的高碼速率pcm信號，設計並製作了一種適用的pcm解調板，能夠從pcm碼流中恢復出位時鐘信號，從而與發送端保持位同步和幀同步，從而對pcm碼流可靠地解調、緩存，並能根據計算機設定的觸發條件自動地捕獲多路信號的有效段，然後利用rs485總線將這些數據可靠地遠傳至計算機以供顯示、分析和保存。
  7. And software method can resolve d channel ' s work for its less data communication ; 3 ) cpu 80c152 is synchronized with mc145572 by a simple synchronous circuit, avoiding the complex fpga interface circuit ; 4 ) data transmission use dma, which reduces the delay of data transmission and cpu occupying ; 5 ) 8bit software look - up table method can achieve 16bit crc quickly, which reduces the resource of both hardware and software

    對通信數據量相對小的d通道，採用軟體實現裝幀與解幀。第三，採用結構簡單的外部同步時鐘電路實現80c152和接入晶元mc145572的同步傳輸，巧妙地避開了復雜的fpga介面電路。第四，利用dma技術完成數據快速收發，降低了數據傳輸時延及cpu佔用率。
分享友人
分享到 Line

分享到臉書