時分電路 的英文怎麼說

中文拼音 [shífēndiànlù]
時分電路 英文
time division circuit
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 分 : 分Ⅰ名詞1. （成分） component 2. （職責和權利的限度） what is within one's duty or rights Ⅱ同 「份」Ⅲ動詞[書面語] （料想） judge
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 時分 : 時分time:黃昏時分 at dusk; at twiligh; cock-shut time
  • 電路 : [訊] circuit （ckt）; electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...
  1. Most of vlsi circuits are sequential circuits. sequential circuits can be simulated by symbolic finite state machine ( fsm )

    Vlsi系統中大部分是時序電路，時序電路可以用符號化的有限狀態機（ finite - state - machine ，簡稱fsm ）來模擬。
  2. Chapter 3 treats the algorithm implementation of demodulator in the receiving asic of dvb - s. in detail, demodulation includes carrier recovery and symbol synchronization. together with the transmission characterization of band - limited input signals the chapter proposes a scheme for implementing carrier recovery loop

    解調具體分為載波恢復、時鐘同步兩大部分，本章著重論述了載波恢復的原理並結合dvb - s輸入信號傳輸特性，提出了相應的實現方案，對部分電路進行了性能分析。
  3. Analysis of 555 timer circuit connected to an exterior control voltage

    外接控制電壓的555定時器電路分析
  4. Automatic water - measuring meter is the combinative production of traditional method and present cmos integration circuit technology. it consists of water - level sensor and mainframe circuit. on the basis of analyzing its application, this paper gives the design of mainframe circuit, including time circuit, time - sequence circuit, input - interface circuit, switch circuit and power circuit

    本文在分析cmos集成電路應用的基礎上，給出了自動量水儀表主機電路的設計，包括定時電路、時序電路、輸入介面電路、開關電路和電源電路的設計；其次，對水位傳感器進行了研究，分析了水位傳感器的工作原理、測量使用條件、動態特性、靜態特性以及水位傳感器的率定、標定方法。
  5. Its innovation is to extend existed fanout - free region pwtitioning methods of combinational circuits to synchionous sequentia1 circuits, and combines fanout source fault simulation and critical path tracing. experimental resu1ts reveal that the efficiency of it is better than that of generic word - level fault parallel fs algorithms

    該演算法的創新在於擴充了現有的組合電路無扇出區劃分方法，使之對時序電路適用，並把它與扇出源故障并行模擬和臨界路徑追蹤方法相結合。
  6. Firstly, the task, structure, technology and function of the existing dispatch system were introduced, whose key technology is based on the tdm and time division switch like pstn. further, the developing direction of pstn is based on ip, the pocked switch system and network, and also the dispatch system of the manned space flight launch base will transmit multimedia information on ip

    首先，介紹了現有調度系統的任務、結構、技術和功能，可以看出，其技術核心是時分多路復用和時分交換技術，現在公用交換電話網（ pstn ）正向基於ip的包交換系統和網路發展，載人航天發射場調度系統也將利用ip網路技術傳輸多媒體指揮信息。
  7. Based on the above analysis results, the system design is finished. the system design principal is detailed. the system architecture and data transmission proctocal are discussed. in order to transmit multi - channel data simutaneously on the monacable, tdm ( time division multiplexing ) technique is adoped in the system design. a special code is designed for data transmission on the tool - bus, so that the too - bus can both supply power and transmit data

    包括單芯電纜數據傳輸系統的設計思想、結構設計和數據傳輸協議的制定。在單芯電纜數據傳輸系統設計中，採用時分多路復用技術，實現多種參數儀器數據的同時傳輸。在儀器總線上採用特殊的碼進行數據傳輸，使得儀器總線既能供電又能傳輸數據。
  8. The automatic test vector generation method based on fault simulation is described, and the whole procedure of atpg of sequential circuits is analyzed, fault simulator - hope as an example

    本文闡述了基於模擬的自動測試生成方法，以故障模擬器? hope為例分析了整個時序電路自動測試生成過程。
  9. Low - power oriented design techniques include selecting low - power parts, low operation voltage, managing clock of mcu or making mcu turn into dormancy, managing power supply of circuit and so on

    低功耗設計的關鍵技術包括選用低功耗的各類器件，低工作電壓，對mcu進行時鐘管理或休眠，對各部分電路和器件進行電源管理等。
  10. Vi techniques are analyzed. the hardware platform and software framework are generalized and specified, a designing plan is put forward. based on this plan, this paper designs power source, amplifying circuit, comparing circuit, count circuit, memory circuit of t module

    對虛擬儀器技術進行了分析，總結評述了其硬體平臺和軟體框架，提出了測速儀模塊的總體設計方案，根據此方案本文設計了測速儀模塊的電源、放大電路、比較電路和計時器電路、數據存儲電路。
  11. Since high performance control logics are usually hard for non - scan test generation, dft structures could be embedded as offsets in tradition, while it will cause manufacturing cost increase and performance overhead. in this paper, an indirect test generation method based on retiming is proposed, which could dramatically reduce the cost of non - scan atpg without any loss of original optimized attributes. experiments on some iscas 89 benchmarks show the benefits of our approach in enhancing atpg of performance - driven logic

    對性能驅動控制邏輯進行測試生成難度較大，通常要加入可測性結構，但會影響原電路優化性能並增加生產成本.本文以重定時理論為基礎，提出了對高性能時序電路進行間接測試生成的方法，這種方法在不影響原電路任何優化特性的前提下，可顯著降低測試生成時間，提高測試生成質量.在iscas 』 89部分基準電路進行實驗，結果證明了其有效性
  12. It consists of two parts : channel modulator ' s controlling system and the receiver ' s controlling system, including the interface designing of the demultiplexer, the controlling of the channel demultiplexer, if modulator, tuner, the setting and transmitting of the system parameters, and the real - time monitoring of the whole system, etc. based on the descriptions of the scheme of bdb - t and the principles of controlling circuits, this paper presents the hardware and software designing methods of the controlling circuits, and realizes a powerful, multifunctional and reliable controlling system which can automatically record the operational states of the system and communicate with other personal computers through a rs - 232 serial interface

    控制系統是實現整個傳輸系統的關鍵部分，它分為通道調制器控制系統和接收機控制系統兩大部分，其中包括了通道解復用器用戶介面設計、對通道解復用器的控制、系統傳輸參數的設置與傳送、中頻調制器的配置、數字調諧器的配置，以及對整個系統的實時監控。本文在闡述了bdb - t方案及其各部分電路的控制原理的基礎上，詳細描述了控制系統的硬體電路設計和軟體實現方法，實現了一套功能完善、性能穩定且具有自動記憶功能的控制系統，同時該系統通過rs - 232串列介面可以實現與計算機的串口通信。
  13. As emphasis, we propose a new backward width - flrst search circuit partitioning method with flip - flop as core for synchronous sequential circuits. and then based on it, we develop a new circuit parallel tg algorithm

    最後重點對電路并行方法進行了研究，提出了一種新的以觸發器為核且消除大功能塊之間反饋的寬度優先反向搜索同步時序電路劃分方法。
  14. Test vector generation based on ant algorithm is presented and implemented, the pheromone computation formula for sequential circuits and status transfer rules are given, and the test results are compared with the results of the other existing test generators - hitec, gatest, cris, digate and strategate, based on standard sequential circuits iscas ' 89 and other synchronous sequential circuits

    提出並實現了基於螞蟻演算法的測試矢量生成，給出了針對時序電路測試矢量生成的信息素計算公式和狀態轉移規則。在iscas 』 89標準時序電路和幾個同步時序電路上實現了測試生成，並將生成結果和其它現有測試生成器（ hitec ， gatest ， cris ， digate ， strategate ）的生成結果作了比較、分析。
  15. In time signal processing, we present a time examination method named digital middle point examination, and simplify the circuit

    在定時信號提取中提出了一種數字化的中點檢測法，簡化了信號處理部分電路。
  16. The thesis includes the design of hard circuit, pcb ( printed circuit board ), driver and application soft involving a / d board and d / a board. the detailed functional modules consist of multiplex signals select module 、 analog digital conversion module 、 digital analog conversion module 、 pci protocol conversion module 、 driver and magnifying module 、 control logic 、 clock circuit and configuration circuit. the importance of the thesis is a / d board

    本課題包括硬體電路、印刷電路板（ pcb ） 、驅動程序和應用軟體的設計，涉及a / d板和d / a板兩大塊部分，具體的功能模塊包括多路信號選擇模塊、模數轉換模塊、數模轉換模塊、 pci協議轉換模塊、驅動放大模塊、控制邏輯、時鐘電路和配置電路，其中重點是a / d板部分。
  17. In the design of neutron monitor device, a part of circuit is programmed into a chip, which improves the performance of neutron monitor device and reduces the area of pcb greatly

    在中子監測儀的設計中，由於部分電路集成到同一個晶元內，使得中子監測儀工作性能大大提高，同時電路板的面積也大大減小。
  18. The hardware design section mainly introduces the circuit design, including the peripheral circuit design of pm5366 and pm4329 and the design of clock circuit and interrupt circuit

    硬體設計部分主要介紹電路的設計，包括pm5366和pm4329的電路設計，以及時鐘電路和中斷電路的設計。
  19. This system is realized by cpld which can get rid of the disadvantages in one - time design including property liable to jamming, long sampling period, and poor working stability. its sampling period is up to 500ns at least and output delay is only 19. 5ns. a stable period of pulse coming out of quadruple - frequency differential circle belongs to it

    完成了用vhdl硬體描述語言對全數字轉速位置測量子系統的設計，並用max ? plusii軟體進行了編譯和波形模擬，在cpld （ max7000 ）得到實現，該系統克服以往設計中存在的易受干擾、工作穩定性差、采樣周期太長等的缺點，輸出延時僅為19 . 5ns ，采樣最低周期可達到500ns ，且四倍頻微分電路獲得的脈沖周期穩定。
  20. Some theoretical extensions are first made in this paper, with the following concepts, theorems and models presented - partial derivative and high - order partial derivative of waveform polynomial for describing the relation between input transitions and output transitions and redefining circuit sensitization ; the concept of waveform polynomial vector for describing a circuit with multiple inputs and outputs, especially for the unified description of circuit modules ; a sensitization theorem for sequential circuits for the purpose of exact timing ; theorems for transition numbers in circuits used to solve problems on noise, power consumption and etc ; waveform polynomial description for sequential circuits used to give a unified form for the function and timing behavior of a sequtial circuit ; and a data structure of generalized list for the representation and manipulation of waveform polynomial

    波形多項式偏導和高階偏導的新概念，用來精確描述輸出跳變與輸入跳變之間的關系，並在本文中用來重新定義了電路的敏化和冒險；波形多項式向量的概念，用於形式化描述實際中的多輸入多輸出的電路，特別是用於統一描述電路模塊的功能及定時行為；時序電路的敏化定理，用於時序電路精確定時分析；波形多項式描述跳變及跳變數的定理，用於噪聲、功耗等問題的描述；時序電路的完整波形多項式描述，用於時序電路功能和定時行為的統一描述；波形多項式的多項式符號表示和運算的模型以及數據結構，用來實現對波形多項式比較有效的描述和運算。
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