時基電路 的英文怎麼說

中文拼音 [shíjīdiànlù]
時基電路 英文
time base circuit
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 電路 : [訊] circuit （ckt）; electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...
  1. This paper mainly aims at the characteristics of the hardware and software structure of the parallel computer on satellite, and has fulfilled researches of fault tolerant technique in three aspects of control theories and engineering : the first research of the system level fault - tolerant module is based on the system structure of the parallel computer on satellite, a kind of cold backup module and a kind of hot backup module for multiprocessor computer have been put forward. then the research of software fault tolerant technique which is based on the operate system named rtems has been carried, the mission level fault - tolerate arithmetic and the system level fault - tolerate mechanism and strategies based on the check point technique have been put forward, at the same time the self - repair technique of software which has used the technique of system re - inject has been studied. finally the technique of components level fault - tolerant based on fpga has been studied, a kind of two level fault - tolerant project which aims at the fault - tolerant module of the parallel computer on satellite has been put forward, and the augmentative of circuit that project design realization need is little, this project can avoid any breakdown of any part logic circuit of the fpga

    本課題主要針對星載并行計算機體系結構及軟體結構的特點，從如下三個方面進行了容錯控制理論研究和實踐工作:首先進行了基於星載多cpu并行計算機體系結構的系統級容錯模型研究，提出了一種多cpu冷備份容錯模型和一種多cpu熱備份容錯模型;然後進行了基於rtems操作系統的軟體容錯技術研究，提出了任務級容錯調度演算法以及基於檢查點技術的系統級容錯恢復機制和策略，同時研究了利用系統重注入進行軟體在線自修復的容錯技術;最後研究了基於fpga的部件級容錯技術，提出了對容錯模塊這一星載并行計算機關鍵部件的兩級容錯方案，實現該方案所需增加的電路少，可避免板級晶元以及fpga晶元內部任何邏輯發生單點故障。
  2. The local network resoure management system is mainly engaged in the lacal network resoure management, at the same time and the network quality managerment as well, also including network line - pipe management, equipment management, configure management, topology management, attemper management and systimatic analysis, the main equipments include pdh, sdh, dwdn, idlc, pon, fwa, adsl, bits etc. by means of the main equipments " s resoure attemper and running state, we can finds out something abnornal in operation, from the whole point of local network, adjusting network is to be made to reach overal optimiztion. ensuring the network operating quality, realizing the the dispatching solution on the basis of network resource management and circuit closed - loop dispatching circulation

    本地網網路資源管理系統是側重於本地網網路資源的管理，同時兼顧網路質量管理。重點網路管線管理、設備管理、配置管理、拓撲管理、調度管理以及統計分析，主要設備包括pdh 、 sdh 、 dwdn 、 idlc 、 pon 、 fwa 、 adsl 、 bits等。通過主要設備的資源配備和運行狀態，該系統發現處理運行異常，從本地網全局的角度調整網路達到整體優化，保證網路的運行質量，在網路資源管理的基礎上，實現調度方案的生成，以及電路通道的閉環調度流程。
  3. The method of connecting timing into 1ogic i s explained in waveform po1ynomia1 on the basis of waveform concept in boo1ean process theory. and an ana1ytica1 de1ay mode1 that is close to practice circuits is found

    並在布爾過程論中定義波形的基礎上，說明了邏輯與時序在波形多項式中的結合方法，建立了接近實際電路的解析延遲模型。
  4. In the next place, by studying the change of the resonant frequency of the whole system, this paper designs the circuit to track the resonant frequency of the system by cd4046 mainly. at the same time, in order to improve the efficiency and get better dynamic capability of the converter, we choose pll and fuzzy control after comparing the pll circuit, fuzzy circuit and pll ? fuzzy control circuit. in the end, this paper brings forward the control blue print to realize the drive control circuit of the high frequency converter, using the dsp chip as the key part to realize four routes of pwm drive pulses with dead band of the control system

    其次，通過對整個系統諧振頻率變化的分析和研究，設計了以鎖相環cd4046為核心的鎖相環控制電路，同時，在綜合比較鎖相環控制、模糊控制以及模糊控制和鎖相環復合控制三種控制演算法的基礎上，進行了系統模擬，得出採用復合控制可使跟蹤電路既具有鎖相環路較好的穩態性能，又擁有模糊控制較好的動態性能，系統魯棒性能好，同時也提高了逆變器的效率。
  5. This paper, on base of analyzing and comparing the correlational measure and control product of domestic home and overseas, achieves real - timely inspecting and measuring every parameter of ergograph with more advance technology of computer measure and control and a method that software can achieve the function in substitute of complex hardware circuit

    本文在分析和比較國內外相關的測控產品的基礎上，採用了較為先進的計算機測控技術，以軟體方法代替以往需要復雜硬體電路才能實現的功能，能夠對測功機的各項參數的實時檢測。
  6. In the sub block circuit design, the contents that the author had introduced include : the principle of band gap voltage reference and the design technique in low power supply ; the analysis of spike pulse noise rejection, frequency divider and dead time in oscillator and control circuit ; the selection of the width and length ratio of four switches and 2x / 1x mode change point in driver and mode selection circuits

    在子電路設計中，作者比較深入分析的內容有:基準電路的原理及低電源電壓下基準電路的設計;振蕩器和控制電路中尖峰脈沖噪聲抑制、兩分頻電路及死區時間設定;驅動及模式選擇電路中開關管的寬長比的選擇及模式轉換點的設計。
  7. One is based on vco, and the other is based on frequency divider. the advantages and disadvantages of them are discussed in the thesis. furthermore, a method of realizing dead time changeable circuit is given, which makes the designed driving circuit have more latitude when it is used

    此外，論文還設計了兩種驅動信號產生電路，一種基於vco ，另一種基於振蕩器和分頻器，並對比了兩者的優缺點;給出了一種死區時間可變的電路實現方案，使所設計的驅動電路使用時具有更大的靈活性。
  8. The theories and design principles of each circuit of the spwm three - phase frequency inverter experiment unit are in detail introduced in this thesis. at the same time some experiment results are shown that include the output voltage and current waves when the load is in resistivity, inductivity or asynchronous motor

    文中詳細介紹了spwm三相變頻實驗單元所包含的各電路環節的理論基礎及設計過程，並給出了調試結果，如負載為阻性、感性和異步電動機時，實驗單元輸出的電壓和電流波形。
  9. According to the mean message traversal, the performance of leo / meo mobile satellite communication networks with intersatellite links ( isls ) is analyzed in this paper. three different traffic patterns are used in the analysis. if the isl number per satellite increases, the advantage of packet switch is more significant than that of circuit switch

    本文提出了一種基於信息平均傳輸距離的中/低軌衛星移動通信系統星際鏈路網路性能的分析方法.根據三種不同的業務分佈模型對繁/簡兩種網路的信息過網時延和呼叫丟失率進行了分析.通過增加網路中每個節點星際鏈路的數目可以改善網路的性能，而且這種改善對採用分組交換的系統比採用電路交換的系統大
  10. Flip - flop is the core of sequential circuits, this dissertation designed a synchronous set - reset edge - trigged jk flip - flop based on rt quantum devices, the jk flip - flop has strong function and high speed, and also riches the types of flip - flops in quantum circuits

    所設計的jk觸發器功能強，且與傳統的觸發器相比，基於rt量子器件的邊沿型jk觸發器具有量子器件的功耗低、速度快、電路簡單等特點。本文設計的jk觸發器豐富了量子電路中觸發器的種類，使得量子時序電路的設計更為靈活。
  11. Time base circuit

    時基電路
  12. Systematic inside have adopted the method of time base with timing circuit storing annual examine information, then the traffic management department and the automobile operation unit can manage or supervise automobile easily

    系統內部採用了時基電路定時的方法儲存年檢信息，便於交通管理部門以及汽車運營單位對汽車進行管理和監督。
  13. Automatic water - measuring meter is the combinative production of traditional method and present cmos integration circuit technology. it consists of water - level sensor and mainframe circuit. on the basis of analyzing its application, this paper gives the design of mainframe circuit, including time circuit, time - sequence circuit, input - interface circuit, switch circuit and power circuit

    本文在分析cmos集成電路應用的基礎上，給出了自動量水儀表主機電路的設計，包括定時電路、時序電路、輸入介面電路、開關電路和電源電路的設計；其次，對水位傳感器進行了研究，分析了水位傳感器的工作原理、測量使用條件、動態特性、靜態特性以及水位傳感器的率定、標定方法。
  14. For examp1e, the sort arithmetic so1ves 1eve1 partition of combination 1ogic ; the computing input waveform of sensitized path makes the possib1e of conf1rm the minimum c1ock circ1e ; the cyc1e - - based method for synchronous op tajg1fyjct7 : @ + $ { 4it x sequentia1 circuits improve the speed of waveform simu1at ion

    其中，編排級數法確定了組合邏輯的層次關系；通路敏化輸入波形方法決定了最小時鐘周期；基於周期的同步時序電路的模擬演算法加快了模擬的速度等。
  15. The automatic test vector generation method based on fault simulation is described, and the whole procedure of atpg of sequential circuits is analyzed, fault simulator - hope as an example

    本文闡述了基於模擬的自動測試生成方法，以故障模擬器? hope為例分析了整個時序電路自動測試生成過程。
  16. Base on the existing synchronous sequential circuits fault simulator - hope, the test vector generation method of sequential circuits based on ant algorithm is systematically researched firstly

    本文在同步時序電路故障模擬器? hope的基礎上，率先對基於螞蟻演算法的時序電路測試矢量生成方法作了系統的開拓性研究。
  17. Since high performance control logics are usually hard for non - scan test generation, dft structures could be embedded as offsets in tradition, while it will cause manufacturing cost increase and performance overhead. in this paper, an indirect test generation method based on retiming is proposed, which could dramatically reduce the cost of non - scan atpg without any loss of original optimized attributes. experiments on some iscas 89 benchmarks show the benefits of our approach in enhancing atpg of performance - driven logic

    對性能驅動控制邏輯進行測試生成難度較大，通常要加入可測性結構，但會影響原電路優化性能並增加生產成本.本文以重定時理論為基礎，提出了對高性能時序電路進行間接測試生成的方法，這種方法在不影響原電路任何優化特性的前提下，可顯著降低測試生成時間，提高測試生成質量.在iscas 』 89部分基準電路進行實驗，結果證明了其有效性
  18. Test vector generation based on ant algorithm is presented and implemented, the pheromone computation formula for sequential circuits and status transfer rules are given, and the test results are compared with the results of the other existing test generators - hitec, gatest, cris, digate and strategate, based on standard sequential circuits iscas ' 89 and other synchronous sequential circuits

    提出並實現了基於螞蟻演算法的測試矢量生成，給出了針對時序電路測試矢量生成的信息素計算公式和狀態轉移規則。在iscas 』 89標準時序電路和幾個同步時序電路上實現了測試生成，並將生成結果和其它現有測試生成器（ hitec ， gatest ， cris ， digate ， strategate ）的生成結果作了比較、分析。
  19. Based on a sequential word - level fault parallel fs algorithm, we develop a multi - processor fault parallel fs algorithin and a multi - processor pattern parallel fs algorithin

    並設計了針對同步時序電路的基於單機字級故障并行fs演算法的多機故障并行fs演算法和基於確定性演算法的多機測試碼并行fs演算法。
  20. This dissertation puts forward an accurately modeling approach. these two kinds of interferences have different sources and spreading path. their simple time - domain model and frequency - domain model are built in this dissertation too, which provides theory foundation for qualitative and quantitative emi analysis

    功率變換器的傳導emi以差模干擾和共模干擾兩種模式存在，在對器件和pcb板高頻建模的基礎上，本文提出了建立差模干擾和共模干擾的精確的時域電路模型的方法和步驟。
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