時鐘線 的英文怎麼說

中文拼音 [shízhōngxiàn]
時鐘線 英文
clock line
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 線 : 名詞1 （用絲、棉、金屬等製成的細長的東西） thread; string; wire 2 [數學] （一個點任意移動所構成的...
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  1. The clock circuitry has also been built into the 8085.

    時鐘線路也裝入了8085中。
  2. At the moment when the hand of the massive time - piece, representing endymion asleep, pointed to nine on its golden face, and the hammer, the faithful type of mechanical thought, struck nine times, the name of the count of monte cristo resounded in its turn, and as if by an electric shock all the assembly turned towards the door

    當金面大時鐘上的時針指到九點，當機械的鐘錘敲打了九下的時候，司儀報出了基督山伯爵的名字，象觸了電一樣，全場的人都把他們的視線轉向了門口。基督山伯爵穿著黑衣服，象他往常一樣的簡單樸素。
  3. Going in the other direction, an intel p4 or amd athlon running at clock speeds over a gigahertz should be able to satisfy the requirements of a 45 megabit t3 line

    另一方面，以超過1ghz的時鐘速度運行的intel p4或amd athlon應該能夠滿足一條45兆位t3線路的需求。
  4. One 1995 microprocessor uses this deeper pipeline to achieve a 300 - megahertz clock rate

    一臺1995年生產的微處理器用這種更先進的流水線操作可達到300兆赫的時鐘頻率。
  5. The speed with which your microcomputer executes programs will vary linearly with the speed of your clock signal.

    你的微型計算機執行程序的速度將與你的時鐘信號的速度成線性關系。
  6. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  7. Thirdly, the paper discusses the driver of the peripheral equipment, how to port the uc / os - n and uclinux, h. 323 protocol and the application of the system in the digital speech classroom. also some software and hardware measure are adopted to enhance the system stability. at last, the shortcoming and the something to be improved are given. dsp can be used to realize real - time speech coding algorithm, and after porting ( ac / os - n, arm can manage the keyboard, the lcd and the ethernet peripheral etc. then the embedded network system with specific purpose can be used in others fields, such as pda, set of top, web tv, ect

    在實際設計實現中，為提高系統軟、硬體整體穩定性和可靠性，使用了以下幾種方法： （ 1 ）低電壓復位、抗電源抖動能力、增加時鐘監測電路、抗電磁干擾能力、散熱等技術； （ 2 ）多層pcb設計，線路板結構緊湊，電源部分採用數字5v 、 3 . 3v 、 3v 、 1 . 8v和模擬5v多電源供電； （ 3 ）選用表面貼和bga封裝的器件； （ 4 ）按照軟體工程的要求進行系統分析，規劃系統框圖、流程分析、模塊劃分，減小了不同模塊的相關性，從而最大限度避免了錯誤的發生。
  8. The analog signals are regulated to satisfy the system and analog - to - digital converter ( adc ) ; dsp is the core part and is connected with adcs, a controller of ethernet, a rs - 485 bus transceiver, a can bus transceiver and a clock. the real - time data is disposed by dsp and is transferred to the upper computer when the alarm is happened

    模擬信號調理模塊對輸入的信號進行調理，以達到系統和模數轉換器（ adc ）采樣的要求; dsp作為系統的核心部件，外擴了adc 、以太網控制器、 rs - 485總線收發器、 can總線收發器和時鐘晶元， dsp對實時數據進行處理，當報警發生時將實時數據通過以太網上傳給上位機。
  9. Abstract : a new clock - driven eco placement algorithm is presented for standard - cell layout design based on the table - lookup delay model. it considers useful clock skew information in the placement stage. it also modifies the positions of cells locally to make better preparation for the clock routing. experimental results show that with little influence to other circuit performance, the algorithm can improve permissible skew range distribution evidently

    文摘:提出了一種新的時鐘性能驅動的增量式布局演算法，它針對目前工業界較為流行的標準單元布局，應用查找表模型來計算延遲.由於在布局階段較早地考慮到時鐘信息，可以通過調整單元位置，更有利於后續的有用偏差時鐘布線和偏差優化問題.來自於工業界的測試用例結果表明，該演算法可以有效地改善合理偏差范圍的分佈，而對電路的其它性能影響很小
  10. Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo

    本文首先對數字減影血管造影（ dsa ）成像系統的組成結構和數據流向進行了深入研究和分析，並對系統中的數據流向進行了完整的歸納和總結，給出了x線數字成像系統中的高速大容量數據通道的設計方案；在對sdram的控制方式做了深入探討后，給出了實現大容量多條sdram共同工作的解決方案，在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲；通過對pci總線介面的深入研究，優化後端狀態機設計和低層驅動程序開發，給出了完整的pci介面方案實現高速dma數據傳輸，完全可以滿足視頻傳輸要求；深入研究了基於大規模可編程器件的數字系統設計方法，針對通用fifo使能信號漂移、輸出數據難于建立和保持等設計難點，提出了利用fpga中的鎖相環提供多個時鐘相移的信號來提高系統穩定性的解決方案，從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。
  11. Realization of a real - time clock in a flammable gas monitoring system with sixteen conditions by two keys

    十六點可燃性氣體狀態檢測系統中在線兩鍵實時時鐘的實現
  12. Adopts vdsm process technology however two outstanding problems are faced to ic layout design when the feature size reaches to 0. 18 m or lower : 1. timing convergence problem seriously affects the circuits schedule, and the interconnect - delay has exceeded more than 70 % of the total circuits ’ delay. 2. si problem, usually it consists two aspects of ir - drop and crosstalk. these problems often affect the chip function after tapout

    本篇論文就是針對超深亞微米階段soc晶元後端設計所面臨的挑戰，提出了運用連續收斂的布局布線策略，尤其是虛擬原型的設計理論，來快速驗證布局，進而提高布線的成功率，並且提出了一種改進的布局評估模型，提高對soc晶元預測布線的準確度;同時，對于時鐘驅動元件選擇，文中提出了一種基於正態分佈模型來達到更有效的選取。
  13. The software includes the program of communication with a stand - alone module, of the identification code returned from a stand - alone module, of opening / closing door, of display, of identification the key number, of reading / writing device by i2c bus. the main function of fingerprint menjin system used for the safe is to open door by fingerprint

    軟體主要由與指紋識別模塊的通訊程序模塊、指紋識別模塊返回代碼識別程序模塊、開門模塊程序模塊、關門程序模塊、顯示程序模塊、鍵盤鍵號識別程序模塊、按i ~ 2c總線協議對時鐘晶元和串列e ~ 2prom的讀/寫程序模塊等模塊組成。
  14. Gps is a planet wireless conductance system which is global and all - weather, gps can offer high precision time orientation information to infinite user, clock precision reachs 10 ? 6 magnitude 。 not only changes traditional time method of quartz crystal clock, but also replaces wireless shortwave and even more lowfrequency signal and tv signal whose overlay range is limited and low precision, offers advantage to geology field task, achieve automatization and high precision of seismic flow observation

    利用gps授時信號全方位、全天候、連續性、實時性和高精度的特點，以gps信號為基準來校準本地時鐘（晶體振蕩時鐘或原子鐘） ，將gps接收機輸出信號的長期穩定度和恆溫晶振的短期穩定度相結合，應用大規模可編程邏輯器件，設計和實現了由pc104控制的實時在線授時系統。
  15. The precise clock source is crystal oscillator made of 74hc04 ; the mute circuit can conceal the error and solve the problem of noise ; the antenna switching circuit in the receiver is to select one antenna from two which receives signal better. it can improve the quality of the receiving audio signal, restrain the noise effectively and promote the system performance

    高精度的時鐘源是由74hc04構成的晶體振蕩器;靜音電路將出錯的音頻信號進行差錯掩蓋，很好地解決了噪聲問題;接收機採用兩副天線切換工作，提高了音頻信號接收質量，有效地抑制干擾，提升了系統的性能。
  16. The data and clock lines are both open collector

    數據和時鐘線都是集電極開路的。
  17. The host has ultimate control over the bus and may inhibit communication at any time by pulling the clock line low

    主機對總線有最高的控制權，在任何時候通過將時鐘線拉低就可以禁止通信。
  18. When the keyboard or mouse wants to send information, it first checks the clock line to make sure it ' s at a high logic level

    當鍵盤或者鼠標想發送數據時，它首先必須檢查時鐘線，確認它處于高電平。
  19. In mass production items such as tv - sets, vcr ' s and audio equipment, this is not acceptable. in these appliances, every component that can be saved means increased profitability for the manufacturer and more affordable products for the end customer

    而採用i ~ 2c總線僅用一條數據線（ sda ）加一條時鐘線（ scl ）來完成數據的傳輸及外圍器件的擴展，對于各節點的尋址是軟尋址方式，節省了片選線。
  20. The host changes the data line only when the clock line is low, and data is read by the device when clock is high

    只有當時鐘線為低的時候，主機才可以改變數據線（也就是將數據寫入到數據線） 。數據將在時鐘為高電平的時候被設備讀取。
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