時鐘計數器 的英文怎麼說

中文拼音 [shízhōngjìshǔqì]
時鐘計數器 英文
clock counter
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 計 : Ⅰ動詞1 （計算） count; compute; calculate; number 2 （設想; 打算） plan; plot Ⅱ名詞1 （測量或計算...
  • 數 : 數副詞（屢次） frequently; repeatedly
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  • 計數 : count; tally; counting計數卡 numbered card
  1. The counter has been preset to 0000 and as the input "runs, " the counter advances by 1 bit per input pulse.

    計數器預置0000，並在時鐘輸入下計算每輸入一個脈沖計數器便累加10。
  2. The three - order modulator has a 2 - 1 cascaded structure and 1 - bit quantizer at the end of each stage, the modulator is implemented with fully differential switched - capacitor circuits. and then, the discussion will begin by exploring the design of various circuit blocks in the modulator in more detail, i. e., ota, switched - capacitor integrator, quantizer, two - phase non - overlapping clock signal, etc., at the same time, these circuits will be simulated in spectre and hspice. at last, the whole cascaded modulator will do behavioral level simulation by matlab soft and simulink toolbox

    本論文中，首先介紹模數轉換器的各種參數的意義，以及一階sigma - delta調制器和高階sigma - delta調制器的原理;給出解決高階單環sigma - delta調制器不穩定性的方案，引入級聯結構調制器，特別針對級聯結構調制器中的失配和開關電容積分器的非理想特性進行詳細的討論;本設計的sigma - delta調制器採用2 - 1級聯結構和一位量化器，調制器採用全差分開關電容電路實現;同時對整個調制器的各個模塊進行了電路設計，包括跨導放大器、開關電容積分器、量化器、兩相非交疊時鐘等，並利用hspice和spectre模擬工具對這些電路進行模擬測試;最後，利用matlab軟體和simulink工具對整個級聯調制器進行行為級模擬。
  3. Thirdly, the paper discusses the driver of the peripheral equipment, how to port the uc / os - n and uclinux, h. 323 protocol and the application of the system in the digital speech classroom. also some software and hardware measure are adopted to enhance the system stability. at last, the shortcoming and the something to be improved are given. dsp can be used to realize real - time speech coding algorithm, and after porting ( ac / os - n, arm can manage the keyboard, the lcd and the ethernet peripheral etc. then the embedded network system with specific purpose can be used in others fields, such as pda, set of top, web tv, ect

    在實際設計實現中，為提高系統軟、硬體整體穩定性和可靠性，使用了以下幾種方法： （ 1 ）低電壓復位、抗電源抖動能力、增加時鐘監測電路、抗電磁干擾能力、散熱等技術； （ 2 ）多層pcb設計，線路板結構緊湊，電源部分採用數字5v 、 3 . 3v 、 3v 、 1 . 8v和模擬5v多電源供電； （ 3 ）選用表面貼和bga封裝的器件； （ 4 ）按照軟體工程的要求進行系統分析，規劃系統框圖、流程分析、模塊劃分，減小了不同模塊的相關性，從而最大限度避免了錯誤的發生。
  4. Based on these analyses, a more understandable structure of usb was established. secondly, the usb device controller framework was established based on the usb device controller function requirements on clock extracting, protocol layer and data management

    其次，針對usb設備控制器的功能要求，從時鐘提取、事件檢測、協議層、數據處理層通信等方面對其進行了結構設計和詳細設計。
  5. The key to the fft algorithm is the design of butterfly computation and that of the address logic. the whole schema is designed in the top - down design flow and described in the vhsic hardware description language ( vhdl ), basing on these, we do our research on reconfigurable technology. the result indicates that the data processing ability of reconfigurable system improved greatly

    結果表明，可重構系統在數據處理能力方面比以往的系統有了很大的提高，本設計實現的fft重構處理器可工作於60mhz下，完成一個16點fft需要132個主時鐘周期，完成32點fft需要324個主時鐘周期，而且具有一定可重構性，可以方便地將其運算點數進行擴展，或將其他的圖像處理演算法在實時處理系統中實現。
  6. The counter output, which represents a binary number, decreases by 1 any time the counter is triggered by a pulse.

    每當計數器被時鐘脈沖觸發一次時，計數器輸出的二進制數便累減1。
  7. Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo

    本文首先對數字減影血管造影（ dsa ）成像系統的組成結構和數據流向進行了深入研究和分析，並對系統中的數據流向進行了完整的歸納和總結，給出了x線數字成像系統中的高速大容量數據通道的設計方案；在對sdram的控制方式做了深入探討后，給出了實現大容量多條sdram共同工作的解決方案，在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲；通過對pci總線介面的深入研究，優化後端狀態機設計和低層驅動程序開發，給出了完整的pci介面方案實現高速dma數據傳輸，完全可以滿足視頻傳輸要求；深入研究了基於大規模可編程器件的數字系統設計方法，針對通用fifo使能信號漂移、輸出數據難于建立和保持等設計難點，提出了利用fpga中的鎖相環提供多個時鐘相移的信號來提高系統穩定性的解決方案，從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。
  8. The developed apparatus can automatically measure evapotranspiration at setting up interval and memory the data through a 32 kilobyte data storage memory. measured data can be transmitted to personal computer by rs232 series communication interface. apparatus will be trigged at measurement time by a real time chip set in it

    該儀器通過實時時鐘晶元實現間隔採集動作的觸發及時間、日期的計數；利用液晶顯示器（ lcd ）進行顯示；使用它能在無人監管的工作環境下，定時進行蒸散測量並將測得數據自動保存到32k數據存儲器中；再通過rs232串列通訊介面將數據傳送到pc機進行進一步處理。
  9. The third, the whole circuit of digital cmos image sensor is presented. the circuits of pixel array, clock signal generator and sam have been improved on the base of simulation

    再次，我們對整個cmos數字圖像傳感器進行了電路設計，主要包括：時鐘信號發生器，順序移位寄存器和像素陣列。
  10. The counter output, which represents a binary number, decreases by 1 any time the counter is triggered by a pulse

    每當計數器被時鐘脈沖觸發一次時，計數器輸出的二進制數便累減1 。
  11. One of the most promising new technologies to help achieve that goal is a new breed of low - powered microprocessors that can vary the speeds at which they operate

    在執行復雜的計算任務，如連續處理大批的數字數據時，這種處理器以極高的速度，即"時鐘脈沖速度"運行。但是在執行要求較低的任務，如運行一個文字處理器或放音樂時，該晶元能減速。
  12. A drive method of unequalized clock counter in panel display which uses no dissimilarity @ subclass to achieve precision unequalized clock counter correction based on functions approximation theory is proposed. the new method is acquired based on the particular analysis results of the display drive design projects which adopted counter drive method in which the balance between the display image quality and the cost of drive circuit is given. finally, synthesis comparison examples are given

    針對目前以該方法為基礎普遍採用的不同技術方案進行詳盡的分析，根據分析的結果闡明了其在圖像顯示質量和驅動代價方面的優缺點，在此基礎上基於函數逼近理論提出了一種平板顯示器計數器非均勻時鐘驅動方法，該方法在計數器時鐘上採用非相異子集完成高精度的非均勻時鐘計數器校正。
  13. This logic is designed containing input signal delay, event type classification, event pre - scaling and timing logic and works in pipeline mode under control of 20mhz clock which ensures no dead time contribution

    主觸發邏輯在20m時鐘下以流水線的方式工作，保證沒有死時間的產生。第二個例子是任意數字信號發生器的設計。
  14. The counter has been preset to 0000 and as the input " runs, " the counter advances by 1 bit per input pulse

    計數器預置0000 ，並在時鐘輸入下計算每輸入一個脈沖計數器便累加10 。
  15. If the film has been properly loaded, the film speed appears on the lcd panel for about 2 seconds. then, the exposure counter displays “ 1 ”

    如膠卷裝得合適，膠片的速度將在2秒鐘內顯示在液晶屏上，這時，曝光計數器顯示「 1 」 。
  16. The whole pwm circuit contains two subcircuit, the front - end is pwm module that make up of the counter that based on nine mosfet true - single - phase - clock d flip - flop ; the back - end is demodulated module, which is consist of a three order chebyshev low - pass filter used trans - conductor capacitor. all the subcircuits are simulated. at last, an approving simulated result of the whole circuit is given too

    在調制部分，利用九管單相時鐘d觸發器構成計數器，並由此組成了脈沖寬度調制電路，同時給出了在典型溫度下的模擬結果;在解調部分，介紹了低通濾波器從無源到有源的設計方法，設計了三階切比雪夫低通跨導電容濾波器，同樣給出了相應的模擬結果;最後，作為將脈沖寬度調制電路和濾波器作為整體電路，以脈沖調頻波為輸入進行了模擬，取得了令人滿意的結果。
  17. In its digital processing circuit, clock chip with high precision and temperature compensation is uesd as reference clock. high frequency reversible counter is used to count trimmed impulse signal forward or backward and two pathes saw signals are selected timely by multichannel selector

    數字信號處理電路採用高精度、具有溫度補償的時鐘晶元作為基準時鐘，採用高頻可逆計數器對整形后的脈沖信號進行正向或逆向計數，採用高性能的多路選擇器控制兩路saw信號的定時選擇。
  18. In the scheme, not only the rtlinux ' s double kernel structure and its virtual interrupt are adopted, which make the standard linux process as the lowest priority one in the real - time kernel, but also the 8254 is set to work in the one - shot model by using the kurt ' s utime package, which improves the clock frequency of the os and reduces the cpu ' s extra burden

    這種新的實時化方案利用了rtlinux的雙內核體系結構和中斷虛擬機技術，將標準linux進程作為實時內核的一個優先級最低的任務進行調度；同時還利用了kurt中utime軟體包將定時/計數器8254置為one - shot工作模式，從而既提高了操作系統的時鐘頻率，又解決了cpu額外負擔過重的問題。
  19. The third row of the table represents synchronous parallel loading of the register and states that if s1 and s0 are both high, then, without regard to the serial input, the data entered at a is at output qa, data entered at b is at qb, and so forth, following a low - to - high clock transition

    表2中第三行表示計數器的同步平行的加載，和表明如果s1和s0為高電平，那麼它就不是連續輸入，在時鐘由低向高跳變后，在a端的數據輸入則在qa端輸出，在b端的數據輸入將在qb端輸出，等等。
  20. A design method based on the decomposition and multiplexing technique of complex instruction, combined the decoding arithmetic of instruction and a step counter together, sub - step realization method of multiclocks is proposed. the similarities and differences of architecture between fsm and multi - ? ocks are discussed from two aspects, timing and state space

    提出了執行周期復用的指令分解、指令寄存器與步長計數器聯合譯碼，以及多時鐘同步的控制流設計方法；進而從時間和狀態空間兩個角度深入討論了控制流設計中狀態機和多時鐘兩種常見體系結構的異同。
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