模擬編碼器 的英文怎麼說

中文拼音 [mónǐbiānmǎqì]
模擬編碼器 英文
analog encoder
  • 模 : 模名詞1. （模子） mould; pattern; matrix 2. （姓氏） a surname
  • 擬 : 動詞1. （設計; 起草） draw up; draft 2. （打算; 想要） intend; plan 3. （模仿） imitate
  • 編 : Ⅰ動詞1 （編織） weave; plait; braid 2 （組織; 排列） make a list; arrange in a list; organize; gr...
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 模擬 : imitate; simulate; analog; analogy; imitation; simulation模擬艙 boilerplate; 模擬電路 [電學] circ...
  • 編碼器 : （將一項信息變換成一系列數碼信號的電路） coder; encoder; encipheror編碼器方框圖 encoder block diagram
  • 編碼 : encoded; code; coded; encrypt; codogram; coding編碼表 encode table; 編碼程序 builder; 編碼尺 code...
  1. The main computer is programmed under windows, while the assistant computer is programmed under dos. the last, based on the idea of module - structure, the software of the testing system are designed, thus this software system is compatible and transplantable to design again. the experiment of measuring principle is taken : take the xy flat of lathe as the parallel - pole device and adjust the angle of sensor, the rotating - probe can test the felloe mould in scanning way

    藉助虛擬儀器的思想，對測控系統進行了設計：採用光柵尺、光電編碼器測量可動部件的運動量，解析度高、誤差小；採用細分驅動的步進電機裝置，控制性能好；系統實施環境溫度的檢測、補償，提高了檢測精度；基於兩級微機組建測控系統：主機為人機界面，採用windows編程，從機用dos編程，實時性好；軟體設計採用兼容性和移植性好的模塊式結構，便於二次開發。
  2. On one hand, the focal point that the interface circuit is designed lies in lining up the arrangement of the aerial data, have adopted one pair of ports ram to cooperate with the counter and realize the lining up of the data, on the other hand, interface focal point that circuit design transmission of data, part this finish mainly and interface of linkport of dsp, make data transmisst to dsp processor at a high speed, go on follow - up punish

    一方面，介面電路設計的重點在於對天線數據的整理排隊，採用了雙埠ram配合計數器實現數據的排隊，另一方面，介面電路設計的重點是數據的傳輸，這部分主要完成和dsp的linkport的介面，使數據高速傳給dsp處理器，進行后續處理。這個項目按照自上而下的設計流程，從系統劃分、編寫代碼、 rtl模擬、綜合、布局布線，到fpga實現。
  3. Turbo codes represent the new code structures, which consist of pccc ( parallel serially convolutional code ) and sccc ( serially concatenated convolutional code ). in this paper, the background of turbo codes are firstly introduced, which includes the base principle of error correction code 、 block code and convolutional code ; the principle of turbo code and the iterative decoding is secondly expanded ; the key decoding algorithm : a revised map algorithm and iterative decoding theory are detailed ; then, a new turbo code structure : hccc ( hybrid concatenated convolutional code ) is presented, and the capacity of this code method is analyzed, the average capacity upper bound is derived ; at last, this code is simulated on awgn ( additive white gaussian noise ) channel and rayleigh fading channel

    本文首先介紹了turbo碼的背景知識，包括差錯控制的基本原理、分組碼和卷積碼；然後闡述了turbo碼的基本原理，包括turbo編譯碼器結構及迭代譯碼原理；較為詳細地描述了關鍵的譯碼演算法： ?種改進的最大后驗概率（ map ）譯碼演算法及迭代譯碼演算法；提出了一種新的turbo碼結構：混合turbo碼（混合級聯卷積碼） ；並用編碼性能聯合界分析方法對混合turbo碼進行了性能分析，得出了其平均性能上界；並在高斯白噪聲通道和瑞利衰落通道上分別作了一些應用研究及計算機模擬實驗。
  4. In improved uep scheme, the syntax elements belonged to luminance parts and chrominance parts was reassigned to different data partitions. those packets containing syntax elements belonged to luminance parts were got error protection at high level so as to guarantee their correctness during transmitting in error - prone network. simulation has shown that using proposed scheme, the packing tradeoff is decreased 8240 bytes in error - free channel and also the output bits and bit rate of coded video stream are decreased 2. 70kbits and 0. 33 kbps respectively

    模擬實驗表明，本方案能在無噪通道中有效降低編碼器端8240位元組的打包開銷和2 . 70kbit的輸出比特數以及0 . 33kbps的比特率，而在有噪通道中可使解碼輸出重構視頻圖像的視覺質量得到一定程度的提高，亮度分量峰值信噪比可增加近1db 。
  5. According to the request of this subject, we have developed the system hardware and software for the slave device and the inspection software running on the pc. in this paper all of the followings is illustrated detailedly, such as the research on the principles of measurement and its realization, three means of water - level measurement that are separately based on photo electricity coder, pressure sensor and potentiometer ; selection of the microchip, we choose an advanced integrated soc ( system on chip ) microchip c8051f021 as the main controller ; realization of signal sampling, processing and its conversion in the mcu ; application of high precision 16 bits adc cmos chip - - ad7705 in our system, designing its interface with the microchip and relevant program ; using a trickle charge timekeeping chip ds1302 in the system which can provide time norm and designing of its i / o interface and program ; additionally, a 4 ~ 20ma current output channel to provide system check - up using ad421. in the system, ad421, ad7705 and the microchip compose spi bus ; to communicate with the master pc, here we use two ways which are separately rs232 and rs485 ; moreover, there are alarm unit, keyboard unit, power supply inspection unit and voltage norm providing unit in the system

    針對研製任務的要求，課題期間研製了下位機系統硬體和軟體，開發了上位機監控軟體，其中所作的具體工作包括：測量原理的研究和在系統中的實現，在本次設計中用三種方法來進行水位測量，分別是旋轉編碼器法、液位壓力傳感器法和可變電阻器法；主控晶元的選擇，我們選用了高集成度的混合信號系統級晶元c8051f021 ；實現了信號的採集和處理，包括信號的轉換和在單片機內的運算；高集成度16位模數轉換晶元ad7705在系統中的應用，我們完成了它與單片機的介面設計及程序編制任務；精確時鐘晶元ds1302在系統中的應用，在此，我們實現了用單片機的i o口與ds1302的連接和在軟體中對時序的模擬，該晶元的應用給整臺儀器提供了時間基準，方便了儀器的使用；另外，針對研製任務的要求，還給系統加上了一路4 20ma模擬信號電流環的輸出電路來提供系統監測，該部分的實現是通過採用ad421晶元來完成的，本設計中完成了ad421與單片機的spi介面任務，協調了它與ad7705晶元和單片機共同構成的spi總線系統的關系，並完成了程序設計；與上位機的通信介面設計，該部分通過兩種方法實現： rs232通信方式和rs485通信方式；系統設計方面還包括報警電路設計、操作鍵盤設計、電源監控電路設計、電壓基準電路的設計。
  6. Based on the realization of the encoder / decoders, this scheme aims at the highest rate downstream frame, and has realized the parallel fec circuit and scrambler complying with the protocols and maken a simulation. the fprme decoder is advanced in the world. the parallel fec circuit completely conforms to the itu - t protocols, and has important practical value

    在rs （ 255 ， 239 ）硬體編碼器/解碼器實現的基礎上，本文按照gpon協議要求，針對gpon中最高速率2 . 488gbps的下行幀，通過設計復雜的操作時序，實現了符合協議規定的32位并行fec編解碼和解擾碼電路，並作了模擬。
  7. On the basis of designing the serial structure of mq encoder, parallel structure of mq encoder is designed using pipelining technique and the coding rate is approximately 1bit / cycle

    為了得到更高速率的mq編碼器，採用流水線結構設計了并行的mq編碼器。模擬結果表明mq編碼器的編碼吞吐量明顯提高，達到了硬體規模和編碼效率的平衡。
  8. With the computer controlling the output of the digital signals and the analog signals, controls and adjusts startup, stop, turn and rotational rapidity of the transducer - electromotor and the strength of brake actuator ; installs the torque sensor on dynamical axis, and installs the encoder on non - dynamical axis of the dimensional globoidal indexing cam mechanism ; utilizes the virtual instrument language labview development the test and control system, with the computer real - time monitoring, late displays and storages the data of the test, and processes the data and analyses it

    利用計算機控制數字量輸出和模擬量輸出來達到控制和調節變頻電機啟停、轉向、轉速;控制制動器的啟停和加載力;在弧面分度凸輪的加載軸和空軸上安裝扭矩傳感器和編碼器;應用虛擬儀器語言labview開發試驗臺的測控軟體系統，用計算機進行實時監測與事後顯示與存儲，並進行信號處理與分析。
  9. True to simulate clearing the internal state of the encoder after the calculation ; otherwise,

    如果要在計算后模擬編碼器內部狀態的清除過程，則為
  10. Hence, the requirements of the servo control card are getting much sophisticated. in this thesis, the research work and implementation details of a 6 axes servo control card are discussed. this card is based on the ti company ? dsp chip tms320f240 and has realized the following functions : a ) signal encoder, b ) position limit, c ) dual ram communication with cpu, d ) coordinated control e ) dia conversion

    該卡以ti公司的16位定點數字信號處理器tms320f240為核心晶元，實現6路編碼器信號輸入處理，軸限位中斷處理，通過雙埠ram與pc進行通訊，接收pc發送過來的控制指令和數據，完成插補運算、聯動運算等控制，通過d / a轉換電路，將結果轉化為模擬電壓送伺服放大器驅動電機。
  11. Simulation has shown that the proposed scheme can achieve more accurately in similarity examination than scheme which proposed by [ 102 ]. so the bit number of coded video stream was decreased about 22. 95 percent and thus the compression ratio was improved. although the coding cost was increased about 8. 25 percent by using proposed scheme

    模擬實驗表明，與文獻[ 102 ]方案相比，提出的方案雖然增加了約8 . 25的編碼器編碼耗時，卻有效提高了對視頻序列突變幀的檢測精度，從而進一步降低編碼器端輸出編碼視頻流的比特數達22 . 95左右，在基本不影響重構視頻信息視覺質量的同時提高了編碼器的壓縮效率。
  12. 3. the coder class is defined introducing the object oriented programming, the important member function is realized such as the beginning and end of coding, the getting of image type, the conversion of image type etc. according to the bandwidth of different users, the bitrate is adjusted and the algorithm is simulatively realized

    採用面向對象的程序設計思想和方法，定義了編碼器類，給出了重要成員函數如編碼開始、編碼結束、獲取圖像類型、圖像類型轉換的程序實現；根據用戶帶寬的不同，調整編碼時用到的位率並且進行了程序的模擬實現。
  13. On designing of the encoder, by using the decoding for video chip saa7113 made in philips, analog video signal inputted realizes a / d conversion in analog / power block

    編碼器的設計中，模擬/電源塊主要實現的功能是對輸入的模擬視頻信號進行a / d轉換，解碼晶元採用philips公司saa7113 。
  14. In paper we designed the processing circuits of magnetic encoder, designed the magnified circuit, the signal collection circuit and the d / a conversion circuit are designed. then magnetic encoder can output two different type signals : digital signals and analog signals, the two type signals are corresponding

    對磁編碼器的信號處理電路進行了設計，設計了磁頭的放大比較電路、單片機信號採集電路和d a轉換電路，設計了單片機信號採集和d a部分的程序，使編碼器能在輸出數字信號的同時輸出與數字信號一一對應的模擬信號。
  15. Chapter 5 gives the design illumination of the rs coder and decoder based on fpga. then it gives the integrated results for realization design of the rs ( 31, 15 ) error - correcting code. after that, it gives the functional and layout simulation results for the limited field multiplier, divider, rs coder and rs de - coder

    第五章給出了基於fpga實現的rs編碼器和譯碼器設計說明， rs （ 31 ， 15 ）糾錯碼設計實現的綜合結果，有限域乘法器、除法器、 rs編碼器、 rs譯碼器的功能模擬和布局布線后模擬結果，最後總結主要的調試經驗。
  16. In detail, they are bit - interleaved coded modulation ( with iterative decoding ), low - density parity - check codes and stf technology. by the performance analysis of bicm ( - id ), which can make code and modulation optimal separately, and achieve maximum possible coding diversity as well as modulation gain, guidelines for its design and an easy algorithm for siso are proposed. design of capacity - approaching of ldpc codes and efficient encoding of them as well as several kinds of its decoding algorithms are investigated

    具體的講，就是討論了基於比特交織的編碼調制技術，並給出了映射方式的設計準則以及核心模塊siso的一種簡單的f - map演算法；研究了編碼最小漢明距隨碼長線性增加的ldpc碼的幾個方面的問題，包括接近香農限碼子集的度分佈對的設計、有效編碼器的實現和各種譯碼演算法的優缺點，並對基於ldpc碼的bicm應用於ofdm傳輸系統中的性能進行了模擬。
  17. The goal of this thesis is to develop a kind of 2kbps wi speech coder based on waveform interpolation ( wi ) coding at 3. 75 kbps, and have it simulated on computer by c language. in this thesis, the existing wi model has been improved

    本文的主要目標是在現有的3 . 75kbps波形內插（ wi ? waveforminterpolation ）演算法的基礎上，開發一個速率為2kbps的wi編碼器，並用c語言在計算機上模擬實現。
  18. Some property and working parameters about the encoder are tested. the result indicated that : ( 1 ) the objective of design is achieved, the encoder can output two type signals simultaneously

    對編碼器的各項性能進行了測試，結果表明： （ 1 ）智能化磁編碼器達到了設計的要求，能同時輸出準確的數字信號和模擬信號。
  19. Based on the simulation results, the key techniques for the design of turbo codes, including the choice of component codes, the design of interleaver, trellis termination schemes and puncturing methods, are discussed deeply. by measuring the statistical characteristic of extrinsic information from component decoders, new iterative stopping criteria and snr estimation updator are devised. also, it is used to implement synchronization of carrier phase

    本文首先對turbo碼的基本編譯碼原理進行分析，在模擬結果的基礎上對turbo碼設計中的分量碼選擇、交織器設計、編碼器狀態歸零方案以及刪余方式等部分關鍵問題進行探討；通過考察外部信息的統計特性，設計了新的迭代停止準則和snr估計更新器，並利用外部信息實現串聯載波相位同步；最後對turbo均衡進行簡要分析。
  20. It gives some solutions for designing the encoder. various log - likelihood - ratio - based belief - propagation decoding algorithms and their reduced - complexity derivatives for ldpc codes used in dvb - s2 are presented, in order to avoid the “ tanh ” function in the check - node updates

    接著，本文介紹了dvb - s2標準中ldpc碼的特點及編碼方法，給出了通過模擬得到的非規則校驗矩陣，針對編碼器設計中遇到的一些問題提出了改進方法。
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