流水線結構 的英文怎麼說

中文拼音 [liúshuǐxiànjiēgòu]
流水線結構 英文
pipeline organization
  • 流 : Ⅰ動1 （液體移動; 流動） flow 2 （移動不定） drift; move; wander 3 （流傳; 傳播） spread 4 （向壞...
  • 水 : 名詞1 （由兩個氫原子和一個氧原子結合而成的液體） water 2 （河流） river 3 （指江、河、湖、海、洋...
  • 線 : 名詞1 （用絲、棉、金屬等製成的細長的東西） thread; string; wire 2 [數學] （一個點任意移動所構成的...
  • 結 : 結動詞（長出果實或種子） bear （fruit）; form （seed）
  • 構 : Ⅰ動詞1 （構造; 組合） construct; form; compose 2 （結成） fabricate; make up 3 （建造; 架屋） bui...
  • 流水 : 1 （流動的水） running water; stream2 （舊時指商店的銷貨額） turnover （in business）流水搬運作用...
  • 結構 : 1 （各組成部分的搭配形式） structure; composition; construction; formation; constitution; fabric;...
  1. In the search for site - dependent characters, the different design elements can be identified in the language and ideas of the office ' s landscape architecture : the poetic planning approach ; the reutilization of proven design principles ; the archaeological search for original features of a place ; the concept of the garden as a theme garden ; the concept of the " openly architectonic " ; the concept of " emptiness " ; and the " production line " concept

    在追尋場地特性的過程中，賴納?施密特教授及其事務所的規劃思想和設計語言可以歸納為：詩意的規劃方法；已被證實的設計原則的再利用；對場所原有特徵的考古學研究的應用；將花園設計成一個主題式花園的概念；直接利用建築結構組織空間的概念； 「空」的概念； 「流水線」的概念。
  2. Owing to its excellent adaptability to large angle - displacement between two transmission shafts and other characteristics such as large transmission ratio, terse mechanism, high transmission efficiency, cardan cross - pin spindles has been widely used as an important mechanical part in transport machines, metallurgy machines, petrolic machines, heavy machines, etc. as an effective and promising approach to resolve complicated development of modern software, component - based development ( cbd ) is put forward to change the present way of software development by producing software through assembling ready software components and its final target is to realize the industrialization of software development totally

    十字軸式萬向聯軸器能夠很好地適應傳動軸間的較大角位移，而且具有傳遞扭矩范圍大、結構緊湊、傳動效率高、維修保養方便等特點，是一種重要的傳動部件，因此在交通運輸、冶金、重型機械等領域中得到廣泛應用。基於組件的開發是近幾年發展並日益成熟起來的一種軟體開發新方法，其核心思想是以流水線方式、通過組裝組件生產軟體，從而容易實現軟體開發的工業化。
  3. Adsp sharc21060 is one of current digital signal processing boards based on super harvard architecture, and it " s architecture is designed to streamy parallel

    Adspsharc21060是一種基於超級哈佛結構的通用數字信號處理器， sharc的結構被設計為流水線并行處理器。
  4. The crucial trait of risc architecture is that it can fit the pipeline compatibly

    Risc體系結構的重要特點是其便於利用流水線結構進行指令操作。
  5. In this paper, the common used encoding algorithms and basic finite - field opera - tions algorithms are introduced, and the decoding algorithms such as inverse - free ber - lekamp - massey ( ibm ) algorithm, reformulated inverse - free berlekamp - massey ( ribm ) algorithm and modified euclidean algorithm are analyzed in great detail. based on the ribm algorithm, a modified structure and a pipelined decoder scheme are presented. a tradeoff has been made between the hardware complexities and decoding latency, thus this scheme gains significant improvement in hardware complexity and maximum fre - quency

    本文簡要介紹了有限域基本運算的演算法和常用的rs編碼演算法，詳細分析了改進后的euclid演算法和改進后的bm演算法，針對改進后的bm演算法提出了一種流水線結構的譯碼器實現方案並改進了該演算法的實現結構，在譯碼器復雜度和譯碼延時上作了折衷，降低了譯碼器的復雜度並提高了譯碼器的最高工作頻率。
  6. The paper elaborates risc technology characteristic and 5 - stage pipeline architecture and function of the 64 - bit risc cpu, and dwells on 64 - bit vega cpu characteristic, and details the eda technology and the main flow of asic design, and elaborates the operation and exception process of the vega cpu and virtual instruction address " architecture and generation, and details cache architecture and mmu. the master dissertation dwells on virtual address translating into physical address, instruction cache finding address and instruction fetching, too

    詳細的闡述了64位vegacpu的特點，闡述了eda技術和asic設計的主要流程，闡述了vegacpu流水線結構、流水線操作、流水線暫停和異常處理，虛擬指令地址的結構和產生， mmu結構，包括指令tlb結構和虛擬指令地址向物理指令地址的生成流程， cache結構，尋址原理和指令的寫策略，指令高速緩存的尋址原理和結構，以及指令的獲取流程。
  7. Our company is the profession produces the factory house of the metals plastics handicraft product, is a firm gathers the design and manufacturing, in the last years we are positive to set up to expand, the technique is continuously perfect, the product construction renews continuously, having owned the design, paint, make the mold and wash to press, print, throw the light, electroplate, linear production in flowing water in etc. in packing technique equipments, main creation : every kind of copper, iron, stainless steel, aluminum, zinc metal alloy, lead tin metal alloy, acryl, pvc. . etc. material of the badge, medal, key buttons up, the badge of police, memorial chapter, memorial currency, school badge, craft mark card, skin piece mark card, tie clip, knife and fork cutlery, into oil acryl, bottle opener, music speech bottle opener, resemble etc. travels the trophy, the business advertises the promotion gift and craft gift

    本公司系專業生產金屬塑料工藝品的廠家，是一家集設計與製造為一體的供應商，多年來積極創新開拓，技術不斷完善，產品結構不斷更新，已擁有設計、繪圖、制模、沖壓、印刷、拋光、電鍍、包裝等流水線的生產技術設備，主要製作：各種銅、鐵、不銹鋼、鋁、鋅合金、鉛錫合金、壓克力、 pvc等材質的徽章、獎章、鑰匙扣、警徽、紀念章、紀念幣、校徽、工藝標牌、皮件標牌、領帶夾、刀叉餐具、入油壓克力、開瓶器、音樂語音開瓶器、像架等旅遊紀念品，商務廣告促銷禮品及工藝禮品。
  8. The inversionless bm algorithm in rs decoder is implemented with serial mode, which avoids the inversion computation and only needs 3 finite - field multipliers. thus, the complexity of hardware implementation has been mostly reduced. a 3 - level pipe - line processing architecture is also used in the hardware and the coding circuit in rs coder is optimized by using the characteristics of the finite - field constant multiplier

    Rs解碼器的設計採用無逆bm演算法，並利用串列方式來實現，不僅避免了求逆運算，而且只需用3個有限域乘法器就可以實現，大大的降低了硬體實現的復雜度，並且因為在硬體實現上，採用了3級流水線（ pipe - line ）的處理結構。
  9. Modem superscalar microprocessors try to perform anywhere from three to six instructions in each stage

    現代超標量體系結構的微處理器努力在流水線操作的每一步中完成三到六條命令。
  10. The armp, which is controlled by a pipeline mechanism, has excellent real time performance and supports precise interrupt. the armp is compatible to powerpc 603e instruction set architecture ( isa ), and will be implemented by 0. 25 m cmos technique

    該處理器具有自主版權，採用自主設計的流水線結構進行控制，具有優良的實時性和精確中斷的特點，在指令集上與powerpc603e指令集完全兼容。
  11. Second, this dissertation gives an algorithm of object - based fast warping

    然後論文提出了一種流水線結構的基於對象模型的快速warp變換演算法。
  12. By analyzing the realization of range migration, we conclude that the pipeline structure is effective to implement azimuth processing

    通過分析距離遷移校正環節的實現過程，提出用流水線結構完成方位處理並且在并行處理平臺上實現。
  13. Fixed - quatity emu1ation with standard program proves that the construct of the pipeline is with reason, and indicates that the average speedup of the pipeline is 1

    典型程序定量模擬測試證明了該流水線結構的合理性，流水線的平均加速比在1
  14. This paper introduces the history of the gpu firstly, and then it analyses the pipeline architecture of gpu. finally, it introduces several types of program languages of gpu

    本文首先介紹了可編程圖形硬體的發展，然後分析了它的流水線結構，最後介紹了幾種最新的編程語言。
  15. On the basis of designing the serial structure of mq encoder, parallel structure of mq encoder is designed using pipelining technique and the coding rate is approximately 1bit / cycle

    為了得到更高速率的mq編碼器，採用流水線結構設計了并行的mq編碼器。模擬結果表明mq編碼器的編碼吞吐量明顯提高，達到了硬體規模和編碼效率的平衡。
  16. For fast computation of dynamic equations, a special operation unit is referred according to the computing structure of dynamic equations. the pipeline idea is used in this operation unit. there are a adder, a multiplier and a trigonometric function generator in it

    在動力學方程的快速計算方面，根據動力學方程的計算結構提出一種可用於專門計算機器人動力學方程的運算單元，此運算單元採用流水線結構，其運算部分包括加法器、乘法器和一個三角函數發生器。
  17. During the design of vxi - bus serial controller module, the functions of vxi - bus including time - sequence for vxi interface, resource management, interrupt process, bus arbitration, are accomplished. to advance the performance and stability, the fpga technic is used to implement the kerneled code including serial bus time - sequence switching to vxi interface time - sequence, the uart, the parameterized baud generator and “ pipeling frame ”. the handle type of data transfer bus for vxi - bus is researched thoroughly, and the format of serial data transfer is designed

    在vxi總線串列控制器設計中，實現了vxi總線控制器的基本功能，包括vxi總線介面時序、總線仲裁、超時處理等;同時利用先進的fpga技術實現了串列總線時序向vxi總線時序的轉換、通用異步收發器（ uart ） 、參數化波特率發生器、流水線結構等功能模塊;在設計中還深入研究了vxi總線數據傳輸的各種操作類型，制定了串列數據傳輸的編碼格式。
  18. ( 2 ) research the instruction launch strategy, controls correlation processing and data correlation processing of 32 - bit mips ’ s double - launching pipeline. obtained the design modes : static launch, optimized compile instruction, 1st pipeline jump and branch processing and double pipeline four channels front data path. ( 3 ) achievement designs by the platform xilinx ise 5. 2i, uses the verilog hardware description language to carry on the design description to the double - launching

    （ 2 ）對基於32位mips架構雙發射流水線的指令發射策略、控制相關處理和數據相關處理等流水線結構的重要問題進行深入研究，並得出了靜態發射、優化編譯指令序、第一流水線無延遲分支處理和雙流水線四通道前向數據通路等一系列能夠與32位mips架構相匹配的雙發射流
  19. The system - controlled iir filter and fft were realized using fpga in this paper, and modified pipeline structure is adopted to greatly raise the running speed in the system - controlled iir filter. in the same time, it is used that the algorithm of n - point complex to compute 2n - point real data block in the radix - 2 fft. it is different to the normal method in the adoption of pipeline single dual ram for each stage

    論文用fpga實現了系統的受控iir濾波器和fft部分，受控濾波器採用改進的流水線結構，運行速度得到了大幅度的提高，同時運用n點復數dft演算法來計算2n點實數數據，在fpga中實現了基2的1024點復數fft ，同一般的實現不同，採用了流水線式的每級單個雙口ram的方法，節省了ram的容量，經驗證，該設計符合濾波器系統的要求。
  20. The papers in the analysis of the figures orthogonal frequency conversion technology basis, more traditional lut and cordic ( coordinate rotation digital computer ), analysis of the superiority of the latter ; and the use of verilog programming to maxplus ii software for the simulation environment, conducted in fpga devices based on the structure of the cordic simulation of frequency conversion

    本論文在分析數字正交下變頻技術的基礎上，比較了傳統的查表法和基於cordic演算法的結構，分析了後者的優越性;並用verilog編程，以maxplus軟體為模擬環境，在fpga上進行了基於cordic演算法流水線結構的下變頻模擬。
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