浮點乘 的英文怎麼說

中文拼音 [fúdiǎnchéng]
浮點乘 英文
floating multiply
  • 浮 : Ⅰ動詞1 （漂在液體表面） float; drift 2 [方言] （在水裡游） swim Ⅱ形容詞1 （在表面上的） superfici...
  • 點 : Ⅰ名詞1 （液體的小滴） drop （of liquid） 2 （細小的痕跡） spot; dot; speck 3 （漢字的筆畫「、」）...
  • 浮點 : [計算機] floating decimal; floating point
  1. In digital relay, the percentage of noise will increase rapidly with the increase of sampling rate when derivation calculus is substituted by sampled difference term. to solve this problem, a new method using fragment function integrated with the least square algorithm is proposed in this paper. the influence of white noise is greatly reduced and the accuracy of the dead angle calculation is nicely improved after adopting the new method

    在數字式保護中，如果用差分代替求導將導致噪聲的百分比誤差隨著采樣頻率的提高而劇增，本文對此進行了分析並提出了用分段樣條函數最小二乘法來計算電流波形的導數值，以便在提高采樣率的同時降低噪聲誤差的影響，並將其應用於基於32位浮點dsp的新型變壓器保護裝置。
  2. Vol. 121 of the ima volumes in mathematics and its applications, springer - verlag, berlin heidelberg, 2000, pp. 59 - 82. 9 murray j d. mathematical biology ii : spatial models and biomedical applications. 3rd edition, springer verlag, january 2003, pp. 141 - 191

    這樣，在存儲四個浮點數后，旋轉計算時，只需要12次加法和12次乘法將四元組轉為矩陣，並對一個頂點只進行6次加法和9次乘法。
  3. Design of a parameterized floating point multiplier

    一種浮點乘法器的參數化設計
  4. In this paper, a lot of researches and exploration are applied to studying the universality and expansibility of hardware and the arithmetic design and code optimization of software. especially, all of the following arithmetics or conceptions are worked out in the research of software design : self - adaptable compression arithmetic based on dictionary model for data collection system, similarity full binary sort tree, a optimized quick search arithmetic and an improved arithmetic of multiplication in the floating - point operation. and all of the arithmetic are designed with mcs - 51 assembly language. the quick search arithmetic, in which merits of both binary search and sequence search are used fully, are based on the specialty of preorder traversal in similarity full binary sort tree

    特別在軟體設計研究中，提出了適用於數據採集系統的數據壓縮演算法? ?基於字典模型的自適應壓縮演算法；提出了類滿二叉排序樹的定義；提出了基於類滿二叉排序樹的先序遍歷特性的最優化快速查找演算法，它充分利用了折半查找和順序查找各自的優點；提出了浮點運算乘法的改進演算法；並在mcs - 51匯編語言層次上對所有的演算法加以實現。
  5. This paper studies fpu ' s algorithm, data - path, control - path, and implements the integration of the powerpc603e system. this thesis mainly discusses the algorithms and the implementation of the floating point unit in the embedded powerpc603e microrpocessor

    論文的研究工作包括： ?研究浮點演算法，主要包括加減法、乘法、除法、開平方以及cordic （ coordinaterotationdigitalcomputer ）演算法。
  6. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  7. After that, it gives the measures of designing dsp ' s assembler as a part of the dsp ' s software development environment together with the c - compiler. moreover, this paper explores the method of design the floating - point arithmetic unit. referring to the ieee754 - 1985 standard for binary floating - point arithmetic, the algorithm and the behavior description of floating - point adder and multiplier is given, and the simulation and verification is shown at the end of this paper

    此外，本文還對處理器的浮點運算單元設計做了初步的研究，以ansi ieee - 754浮點數二進制標準為參考，借鑒了經典的定點加法器和乘法器的設計，嘗試性的給出了浮點加法單元和乘法單元的實現模型和行為級上的硬體描述，並對其進行模擬和驗證。
  8. A integrated algorithm of ambiguity resolution is proposed. by using triple carrier phase, integer gauss transformations, qr factorization, cholesky factorization, and geometry constraint, the correlation between ambiguity components is reduced, and more error ambiguity can be discarded, also process of ambiguity searching getting rapidly. the ratio test combining constraint of baseline is used to fix ambiguity rapidly

    利用三差最小二乘求解模糊度浮點解，然後採用整數高斯變換降低模糊度分量間的相關性，再根據qr分解和基線幾何約束減少需搜索的模糊度組合，採用cholesky分解在搜索過程中及早淘汰不正確的模糊度組合，最後利用ratio檢驗與基線幾何約束條件相結合檢驗模糊度組合，盡快固定正確的模糊度。
  9. Maglev, regarded as a " green " means of transportation of 21st century, has many remarkable advantages such as comfortable riding, high speed, good environmental adaptability, flexibility and nonpolluting, etc. compared with traditional railway train, maglev is running above the track

    磁浮列車以乘坐舒適、速度快、對地形適應性強、選線較靈活、無污染等特點，被稱為21世紀的綠色交通工具。和傳統輪軌列車相比，磁浮列車是脫離軌道運行的。
  10. On the one hand it is important for the design of floating - point processor unit to optimize speed while algorithms of high - speed are introduced. for examples, two - path of high - speed floating - point addition, booth coding of floating - point multiplication. srt of floating - point division and square root, cordic of transcendental function and so on

    一方面浮點處理部件設計重點在於速度的優化，所以採用優化的高速演算法，如浮點加法的two - path 、浮點乘法的booth編碼、浮點除法和平方根的srt演算法以及超越函數的cordic演算法等。
  11. In a floating - point representation, the numeral that is multiplied by the exponentiated implicit floating - point base to determine the real number represented

    浮點表示法中的一個數字，該數字乘上隱式的浮點底數的冪就決定了所表示的實數。
  12. Any floating - point operation like addition or multiplication is achieved in a few discrete steps

    任何浮點操作，例如加法和乘法，都可以通過幾個步驟來實現：
  13. This thesis estimate the delay of the critical path of an improved floating - point fused multiply - add ( maf ) at a qualitative level, and compare it with the basic maf implementation

    摘要針對一種改進的浮點乘加器結構，對關鍵路徑的延時進行定量的估算，並將其與傳統乘加器結構的延時進行比較。
  14. A number of challenges needed to be met to design and implement a jpeg coding in hardware rather than in software running on a microprocessor. jpeg coding normally requires many floating - point multiplication calculations

    Jpeg需要進行大量的浮點乘法運算，但用硬體實現乘法運算會佔用比實現加法運算多得多的晶元資源。
  15. A quick check of your internet - connected refrigerator magnet tells you your train which travels at speeds up to 250 miles an hour as it electromagnetically hovers above its guide track is a bit behind schedule, too

    趕快查一下電冰箱上的磁貼，那是與網際網路鏈接的。磁貼將告訴你，你所要乘坐的時速達250英里相當於400公里的磁懸浮火車正好也晚點了。
  16. Multiplication and floating - point division

    乘法和浮點除法（
  17. Serial. print ( ) truncates floats into integers, losing any fractional values. it is sometimes useful to multiply your float by a power of ten, to preserve some of this fractional resolution

    丟棄浮點保留整數，這將損失小數值。有時你可以將浮點值乘以10 ，即可保護這些浮點值。
  18. Then, the typical emboss bump mapping is delivered, so is the dot3 bump mapping that is the main techmology used in graphics card. they are discussed fully, which is based on the principle of them. and the pros and cons of them are discussed in detail

    接著介紹了比較典型的浮雕凹凸紋理映射技術和現在主流顯卡採用的點乘凹凸紋理映射技術，從實現的原理入手對二者進行了詳細的論述，並對二者的優缺點進行了細微的比較。
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