浮點運算器 的英文怎麼說

中文拼音 [fúdiǎnyùnsuànqì]
浮點運算器 英文
floating point unit
  • 浮 : Ⅰ動詞1 （漂在液體表面） float; drift 2 [方言] （在水裡游） swim Ⅱ形容詞1 （在表面上的） superfici...
  • 點 : Ⅰ名詞1 （液體的小滴） drop （of liquid） 2 （細小的痕跡） spot; dot; speck 3 （漢字的筆畫「、」）...
  • 運 : Ⅰ動詞1 （物體位置不斷變化） move; revolve 2 （搬運; 運輸） carry; transport 3 （運用） use; wield...
  • 算 : Ⅰ動詞1 （計算數目） calculate; reckon; compute; figure 2 （計算進去） include; count 3 （謀劃;計...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 浮點 : [計算機] floating decimal; floating point
  • 運算 : [數學] operation; arithmetic; operating
  1. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  2. The main research area is the structure optimization of floating - point adder, which is intent to minimize the delay of floating - point addition and optimize the circuit structure

    主要研究方向是優化浮點加法器結構，減小浮點加法運算的延遲，優化電路結構。
  3. After that, it gives the measures of designing dsp ' s assembler as a part of the dsp ' s software development environment together with the c - compiler. moreover, this paper explores the method of design the floating - point arithmetic unit. referring to the ieee754 - 1985 standard for binary floating - point arithmetic, the algorithm and the behavior description of floating - point adder and multiplier is given, and the simulation and verification is shown at the end of this paper

    此外，本文還對處理器的浮點運算單元設計做了初步的研究，以ansi ieee - 754浮點數二進制標準為參考，借鑒了經典的定點加法器和乘法器的設計，嘗試性的給出了浮點加法單元和乘法單元的實現模型和行為級上的硬體描述，並對其進行模擬和驗證。
  4. Binary floating - point arithmetic for microprocessor systmes

    微處理器系統的二進制浮點運算
  5. A processor usually has two sets of general - purpose registers, one optimized for floating - point operations and the other for integer operations

    一個處理器通常有兩組通用寄存器，一組優化為用於浮點運算，一組優化為用於整數運算。
  6. It cost about 313, 000, and in terms of price - performace ratio, this placed the avalon significantly above the 64 processor origin 2000 from silicon graphics, which produced the same crop of gigaflops for a cost of approximately 1. 8 million

    它價值大約31萬3千美元，並且在價格性能比方面，它排在silicon graphics的origin 2000 64位處理器之上，後者有相同數量的gigaflop （每秒十億次浮點運算）而價值大約180萬美元。
  7. This article deals with the method to determine the guard digit in the left normatlization of float point number in the analysis and design of computer system, and briefly introduces its application in practice

    摘要介紹了在計算機系統分析和設計中，用於浮點數左規格化的警戒位的設置方法，並簡要說明了該類警戒位與用於舍入的警戒位共同組成了運算器中的累加器的實際警戒位字長。
  8. This is a mathematical calculator designed for single - hand operation, a key figure refers to each wide support floating - point operations. press vivid and lively design

    這是一個為單手操作設計的數學計算器，每個數字鍵有一指寬支持浮點運算，按鍵設計活潑生動
  9. Become a kind of new electronics circuit - current - mode circuit. it is replacing the traditional design method of the voltage - mode in the high frequency high - speed signal processing realm 。 this thesis mainly discussed the modified second - generation current conveyors based on the current - mode kinds of new cuicuit components, they are stronger modified standard current - mode parts in fuctions on this foundation. mainly including the modified differential difference current conveyor ( mddccii ) 、 the fully balanced second generation current conveyor ( fbccii ) 、 ( full balances ) four - terminal floating nullor ( fbftfn ) and the current differencing buffered amplifier ( cdba ), they are all function very strong standard current - mode parts, they all can provide some circuit functions of better than general operation amplifier, because they have the voltage importation and the current importation, therefore use it since can carry out the voltage - mode signal processing circuit expediently, can also carry out the current - mode signal processing circuit expediently, and have to increase the benefit bandwidth to accumulate more widely than the voltage - mode, but have their advantages more according to the current - mode filter of the modified current conveyor, because it constitutes in brief, the filter wave function is stronger and they are better than in general use operation amplifier of many advantages, be easy to composing for example 、 high speed 、 frequency bandwidth 、 the power supply voltage requests low 、 consume small, the impedance is different from etc. advantages, otherwise they have biggish dynamic range, and flexible circuit synthesize, so they are the best active parts

    從第二代電流傳輸器ccii入手，重點研究了以下幾種改進型的第二代電流傳輸器:改進的差動差分電流傳輸器mddccii 、全平衡第二代電流傳輸器fbccii 、多輸出四端浮地零器ftfn 、全平衡四端浮地零器fbftfn 、電流差分緩沖放大器cdba的電路結構及其模型。然後在此基礎上系統地研究了基於這幾種改進型的第二代電流傳輸器的濾波器的設計方法，主要方法和結果如下:利用mddccii設計了差分式連續時間電流模式低通、帶通濾波器;電流模式跳耦結構考爾低通濾波器;利用fbccii設計了帶通二階節濾波器及電流模式雙二階通用濾波器;設計了基於多輸出端ftfn的電流模式二階通用濾波器電路;通過數字化開關選擇的基於fbftfn的電流模式通用濾波器;設計了基於最少個數電流緩沖放大器（兩個cdba ）的多功能通用電流模式濾波器及其在非理想因素情況下分析。設計濾波器的主要方法是採用級聯設計、運算模擬（信號流圖法）和反饋設計（跳耦法） 。
  10. As a component of high speed float - point calculator, coprocessor is very important to the improvement of the speed and precision of cpu

    協處理器作為高速浮點運算部件，對提高cpu的運算速度、運算精度有著重要的協同作用。
  11. Coprocessor is a crucial part of high - speed and high - precision, whose performance directly affects the capabilities of system floating - point execution

    協處理器作為高速度和高精度的關鍵運算部件，其性能直接影響系統的浮點運算能力。
  12. The primary contents and innovations of this article are introduced below. in order to take advantage of the high speed of calculation, and at the same time, improve the accuracy and dynamic - range of the algorithm, three kinds of multi - input floating point adder algorithm ( fpa ) are summarized and a high - performance multi - input fpa structure is put forward with a self - defined floating point format. the performance of the high - performance structure on calculation speed and logic resource consuming is better than the normal structure

    論文的主要工作及創新點如下:為了充分利用fpga處理速度快的特點，同時盡量提高演算法的精度及動態范圍，本文在對浮點加法器演算法進行深入研究的基礎上，規納總結了三種不同的多輸入浮點加法器演算法，並創造性地提出了一種高效的多輸入浮點加法器結構及一種適合於fpga實現的自定義浮點數格式，這種高效的結構在所需的邏輯資源和運算速度上均遠優于傳統的多輸入結構。
  13. Floating - point unit is a special microprocessor circuitry unit that deals with floating - point arithmetic operations, which is widely used in scientific arithmetic, cpu, dsp ( digital signal processing ) and image processing, the thesis discusses how to implement high - performance floating - point processing unit based on the research of its implementation algorithm and its implementation structure

    浮點運算單元（ fpu ）是處理器中專門進行浮點算術運算的電路單元，廣泛應用在科學計算、 cpu 、 dsp和圖象處理。論文從浮點運算單元的實現演算法和結構的研究出發，討論如何實現高性能浮點運算單元。
  14. Based on s698 technology, obt - devsys - s698 is one of the serial s698 - mil application development systems including 32 - bit embedded processor with 32 64 - bit fpu 160mhz processing speed sram memory controller flash memory controller uart ps 2 led interrupter controller, etc. the bus interfaces is composed of i2c spi magnetic card interface and ic card interface. obt - devsys - s698 carries on the advantages of s698 serial module such as compact structure and reasonable composition

    Obt - devsys - s698是s698系列嵌入式處理器開發板中的一員，其上包括：具有32 64 - bit浮點運算單元的32 - bit嵌入式處理器，主頻160mhz ， sram存儲器， flash存儲器具有三路uart介面，一路ps 2介面， led發光二極體控制電路，中斷操作按鈕其外擴總線包括i2c總線介面spi總線介面磁卡介面智能卡介面等。
  15. At first, we introduce the working flow of ir image processing and the structure of the image processor, then we present the goal of the design : image pre - processing and data communication. in the part of the image pre - processing, the factors causing the nonuniformity of fpas are analyzed particularly, and several. resolutions are presented, which characters are illustrated at last. according to the design requirement, we decided to implement the two - point nonuniformity correction method in fpga

    在圖像預處理部分，首先就紅外成像傳感器非均勻性的成因進行了詳細分析，總結了紅外成像傳感器非均勻性校正的主要方法，分析了各種方法的優缺點；根據成像制導信息處理機實時處理的要求，利用現場可編程門陣列實現了基於浮點運算的兩點法非均勻性校正模塊。
  16. Double is the most efficient data type, because the processors on current platforms perform floating - point operations in double precision

    是最有效的數據類型，因為當前平臺上的處理器以雙精度形式執行浮點運算。
  17. Double is the most efficient of the fractional data types, because the processors on current platforms perform floating - point operations in double precision

    是小數數據類型中效率最高的，因為目前各平臺的處理器都是以雙精度來進行浮點運算。
  18. For performance reasons, the compiler defaults to the common language runtime implementation for floating point arithmetic constraints

    出於性能方面的原因，編譯器在默認情況下使用公共語言運行庫（ clr ）對浮點運算約束的實現。
  19. More calculation already having an huge memory size, all controllers could now manage up memory words and could use double words and floatting point ( with more than 45 new instructions arithmeticc, trigonometric, conversion, . . )

    在已有的大內存容量基礎上，現在的twido控制器可以支持更多的內部字，雙字處理，以及浮點運算；並新增多達45種數學指令，包括算術運算、三角函數轉換等。
  20. This hardware can complete 120 million times float operation in one second. the rate of a / d conversion is up to 500ksps and the precision is up to 16 bits

    該硬體可以實現每秒120兆次浮點運算，採用一片ltc1608進行a d轉換，片內自帶采樣保持器、解析度為16位、轉換率為500ksps 。
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