浮點單元 的英文怎麼說

中文拼音 [fúdiǎndānyuán]
浮點單元 英文
fpu floating point unit
  • 浮 : Ⅰ動詞1 （漂在液體表面） float; drift 2 [方言] （在水裡游） swim Ⅱ形容詞1 （在表面上的） superfici...
  • 點 : Ⅰ名詞1 （液體的小滴） drop （of liquid） 2 （細小的痕跡） spot; dot; speck 3 （漢字的筆畫「、」）...
  • 浮點 : [計算機] floating decimal; floating point
  1. Based on the analysis of thermal contact metamorphic aureoles, granitoid interior structure, quartz axis fabric and strain characters in the different rock unites of yuanshishan granitoid and its wall rocks, the emplacement mechanism of yanshishan granitoid was studied. the magmatic explictite dynamic was advanced in light of regional stress and magma dynamic research. those conclusion was synthesized to ascertain the emplacement mechanism - granitic magma ascended in dikes with the minimum critical width of the magma ascending channels about 2. 213. 88m and located in the core of yindianshan dome with the passive style of dyke explictite ; the later unite is a kind of multiple emplacement mechanism with the character of active emplacement of ballooning

    同時運用巖漿動力學原理從另一個角度探討其侵位驅動力。綜上指出：經分凝后的活動性巖漿在深部側向擠壓和浮力的聯合驅動下，沿深大斷裂以最小臨界寬度為2 . 213 . 88m的裂隙脈動上侵，整體以巖墻擴展的方式被動定位於銀殿山穹窿的核部，但後期屋面前單元具有主動侵位的特點應為一種復合定位機制。
  2. Feu floating point execution unit. this performs floating point related calculations for both existing scalar instructions along with support for some of the new simd - fp instructions

    Feu浮點執行單元。與支持simd _ fp指令的現有規模指令一起執行浮點相關的計算。
  3. The development of single chips and analyzers at home and that of overseas compared, a kind of pocketable dual - channel and multi - function signal analyzer, based on dsp, are researched with the functions of dynamic analyzer, data logging acquisitor, start - up / coast - down analyzer and dynamic balancer, etc. and the functions data acquisition, storage, display and analysis of vibration signal are validated in practice, high - speed float point data calculation ability, large memory space and simple operation are the characteristics

    高性能單片機尤其是dsp功能晶元的採用及用戶技術要求的不斷提高，使得信號分析儀的功能越來越完善，在比較了國內外單片機和信號分析儀的發展現狀后，開發研製了一種基於浮點dsp晶元tms320c32的便攜式雙通道多功能信號分析儀，兼有動態信號分析儀、巡檢數采器、起停車分析儀、動平衡儀等多種儀器的功能。
  4. Fpu : floating - point processing unit

    浮點處理單元
  5. 2 montoye r k, hokenek e, runyon s l. design of the ibm risc system 6000 floating - point execution unit. ibm journal of research and development, 1990, 34 : 59 - 71. 3 oberman s. floating - point arithmetic unit including an efficient close data path

    我們採用90納米cmos標準單元工藝以及synopsys自動布局布線流程進行實驗，實驗結果表明該演算法在高性能雙通路結構的浮點加減運算中引入后，可以使得近路徑的運算延遲整體降低10 . 2 % ，且演算法本身沒有造成新的關鍵路徑。
  6. Fpu float point unit

    浮點運算單元
  7. There are five parts in powerpc603e ? microprocessor : integer execution unit, floating point unit ( fpu ), instruction ( data ) cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way

    Powerpc603e微處理器系統由定點執行單元、浮點單元、指令（數據） cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令。
  8. It has five parts, such as integer execution unit, floating point unit ( fpu ), instruction cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way. the instruction set and i / o signals are compatible with powerpc

    它由定點執行單元、浮點單元、指令cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令，指令集和介面時序兼容powerpc ，是典型的risc微處理器結構。
  9. Returns the specified single - precision floating point value as an array of bytes

    以位元組數組的形式返回指定的單精度浮點值。
  10. After that, it gives the measures of designing dsp ' s assembler as a part of the dsp ' s software development environment together with the c - compiler. moreover, this paper explores the method of design the floating - point arithmetic unit. referring to the ieee754 - 1985 standard for binary floating - point arithmetic, the algorithm and the behavior description of floating - point adder and multiplier is given, and the simulation and verification is shown at the end of this paper

    此外，本文還對處理器的浮點運算單元設計做了初步的研究，以ansi ieee - 754浮點數二進制標準為參考，借鑒了經典的定點加法器和乘法器的設計，嘗試性的給出了浮點加法單元和乘法單元的實現模型和行為級上的硬體描述，並對其進行模擬和驗證。
  11. Resets the floating - point unit ( fpu ), if any

    有浮點單元（ fpu ）的話，將其重置。
  12. Reads the current element value as a single - precision floating - point number

    將當前元素值作為單精度浮點數讀取。
  13. This paper discusses the process of industrial control system that developed from distributed control system to fieldbus control system and its improvement. in the same time, this paper compares rs - 485 and can. this paper analyzes a concrete example to represent this system ' s advantage, such as convenience, common use

    在本論文中，以該應用系統的一個智能化單元? ?浮輥張力控制單元為具體分析對象，詳細描繪其組武漢理工大學碩士學位論文成方式、工作原理、程序設計方法以及工作特點，對比了使用rs 485總線技術進行通信與使用can總線技術進行通信的不同，較好地體現了叢于觀場總線技術的染敝控制系統介實際工業應用中的優拎和特點。
  14. Function ensures the rounding mode of the floating - point unit is toward zero truncate, by setting bits 10 and 11 of the control word

    函數還通過設置控制字的第10位和第11位來確保浮點單元（ fpu ）的舍入模式為向零方向（截斷） 。
  15. Different with traditional microprocessor which solves floating - point normalization with soft ware, the project implemented floating - point normalization with hard ware. the research focused on the architecture of microprocessor mainly

    因本課題意在實現微處理器的基本結構，並未涉及到編譯器，因此在對微處理器的浮點處理單元的規格化演算法進行深入分析的基礎上提出了用硬體實現浮點單元規格化的方法。
  16. Amex86 microprocessor is composed of integer processing unit, float - point processor unit ( math coprocessor ) and protect test unit

    Amex86系統由一個整數處理部件（ cpu ） 、一個浮點處理部件（數學協處理器）和一個保護測試單元組成。
  17. It features a data prefetch engine, non - blocking interleaved data cache, dual floating point execution units, and many other goodies

    它特有一個數據預取引擎，無阻塞的交叉數據緩存，雙浮點執行單元，以及其他一些很好的設計。
  18. According to the task and delay information of the floating - point unit, it was implemented with three - stage pipeline, including pre - normalization stage, calculation stage and post - normalization stage. approximately, the delay of each stage is equal with each other. also, floating - addition, floating - subtraction and floating - multiplication can been implemented by the floating - point unit

    根據浮點單元承擔的任務及延遲信息，採用三級流線實現：前規格化級（ pre - normalizationstage ） 、計算級（ calculationstage ） 、后規格化級（ post - normalizationstage ） ，每一級的工作量和延遲近似相等。
  19. In the project, the microprocessor is composed of integer unit and floating - point unit

    本課題所設計的微處理器共包括兩部分：整數單元和浮點單元。
  20. To decrease the area of the chip, resource sharing, which is a synthesized optimized method of eda tools, was used in the project. the code was verified in fpga soft ware environment. synthesized netlists based on fpga and asic were given in the paper for future work

    本課題所設計的微處理器的整數單元和浮點單元均採用硬體描述語言vhdl進行建模，為降低晶元面積，將資源共享這一eda工具的綜合優化方法應用於設計中，並在現有條件下進行了簡單的fpga驗證，考慮到今後的asic設計，本文給出了基於fpga和基於asic的兩種綜合網表。
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