現用硬體 的英文怎麼說

中文拼音 [xiànyòngyìngtǐ]
現用硬體 英文
off the shelf hardware
  • 現 : Ⅰ名詞1 （現在; 此刻） present; now; current; existing 2 （現款） cash; ready money Ⅱ副詞（臨時; ...
  • 用 : Ⅰ動詞1 （使用） use; employ; apply 2 （多用於否定: 需要） need 3 （敬辭: 吃; 喝） eat; drink Ⅱ名...
  • 硬 : 形容詞1 （堅硬） hard; stiff; tough 2 （剛強; 堅定; 強硬） strong; firm; tough; obstinate 3 （勉...
  • 體 : 體構詞成分。
  • 硬體 : hardware
  1. The basis idea of software radio ( srd ) is to place the a / d and d / a close up the antenna as possible as and use software to realize all the function of any radio based on an opening and blocking currency hardware platform

    軟體無線電的基本思想是將寬帶a / d及d / a盡可能靠近天線，將無線電臺的各種功能在一個開放性、模塊化的通用硬體平臺上盡可能多的用軟體來實現。
  2. According to the research, the major work done is as following : < 1 > analyzes the symmetric - key encryption algorithm des and dissymmetric - key encryption algorithm rsa, and makes them easy to realize in hardware. < 2 > according to the algorithms and the thought of reconfigurable computing, the dissertation accomplishes the design of 64 - bit des system architecture and the design of 256 - bit ~ 1024 - bit rsa system architecture. < 3 > using the top - down high level design methodology and the hdl language, accomplishes the description of the des / rsa designs, the simulation and the synthesis

    本論文主要的研究工作： < 1 >對現有的對稱加密演算法des演算法和非對稱加密演算法rsa演算法進行分析，使其易用硬體實現； < 2 >基於可重構思想和特點，完成64位des演算法和256位1024位模長rsa演算法的可重構硬體的設計； < 3 >採用自頂向下的設計方法，利用hdl語言對des / rsa設計進行功能描述，並完成軟體模擬，綜合和布線； < 4 >在可重構計算驗證平臺上進行演算法驗證，並對設計的可重構和設計的進一步優化進行討論。
  3. For the short of the hardware resources such as ram, the embedded system could not support the full of tcp / ip protocol and it must expurgate the tcp / ip protocol according to different network application

    因此，必須針對不同的網路應用對協議棧進行刪減，保留其基本功能，以滿足網路應用的需要。嵌入式tcp / ip的實現有硬體固化和軟體兩種方式。
  4. Digital image processing consume a large amount of memory and time commonly. basing on the advantage of fpga, the paper design harware module by hdl ( hardware language ), i. e., some function is achieved by les ( logic element ) of the fpga. the real - time of digital image processing is achieved by this. the sample and display of digital image is the important part. so, the paper mainly design the sample and desplay module. the sample card is designed and it ’ s word mode is configured according china ’ s cvbs ( composite video bar signal ). for acquiring the image and storing it correctly to sram, the paper design the sample - control module. the sample module can work correctly using least time. the reliability and real - time achieve the reference. according the vga principle and scheduling of the ths8134, the paper design a vga - control module by hdl. firstly, the control signal is synthesized secondly, the horirontal and vertical synchronization signals is synthesized according to the vga interface standard

    圖像處理的特點是處理的數據量大，處理非常耗時，為實現數字圖像的實時處理，本文研究了在fpga上用硬體描述語言實現功能模塊的方法，通過功能模塊的硬體化，解決了視頻圖像處理的速度問題。圖像數據的正確採集和顯示輸出是其中的兩個重要的模塊，因此，本文主要完成了圖像數據的採集和顯示輸出的設計。本文設計了採集卡，並要對其工作模式進行了配置和編寫了採集控制模塊，在採集控制模塊的控制下，將數字圖像數據正確無誤的存儲到了sram中。
  5. Then, the detailed research and developing process is discussed : the in - system functions implementing in cpld ; hardware modules design of the main controlling board and the customer ' s board ; testing the hardware modules one by one. and then, the software flow chart of the design of call management and telephonist ' s services are introduced

    本文詳細介紹了改型設備的研製過程，包括cpld片內功能設計實現、主控制板和用戶板各功能模塊工作原理和設計實現、各硬體模塊功能測試等，最後給出了局內呼叫處理功能和話務員服務功能的軟體實現流程。
  6. Because period narrow band signals are the main part of background noises, this thesis uses hardware description language to design a multi - band finite impulse response filter ( fir ) and downloads the program into filed programmable gate array to eliminate the period narrow - band interferences in the background noises

    3 ）在現場環境中，背景干擾主要是周期性的窄帶，本文利用硬體描述語言（ vhdl ）設計了一個多帶fir有限沖擊響應濾波器。應用到可編程邏輯器件中，消除了背景噪聲中的周期性干擾，為信號的進一步處理提供盡可能幹凈的信號。
  7. In data management of spherical panorama, several techniques are discussed and cubic is taken as spherical panoramic data structure, for that is simple to implement and convenient to use hardware acceleration while navigate the panorama. in the technique of panorama navigation, texture map technique is applied to display the panorama

    在球面全景圖的數據組織方面，本文討論了各種球面全景圖的數據組織方式，在此基礎上，決定採用立方體來保存球面全景圖，這種方式在實現上比較簡國防科技大學研究生院學位論文一單，也方便在漫遊時使用硬體加速技術。
  8. ( 4 ) on the research of cnc ' s fine interpolate technology, a realization method of fine interpolate based on hardware is proposed, and the design principle and realization technology of high - speed hardware fine interpolator is researched

    （ 4 ）研究了高速數控系統的精插補技術，提出了採用硬體實現高速精插補的策略，並著重研究了硬體精插補器的設計原理與實現技術。
  9. There are two ways to perform successive approximation: using hardware and using software mixed with hardware.

    實現逐次逼近的辦法有兩種：使用硬體以及軟、硬體混合使用。
  10. The hardware design which is the basis of the whole design based on sopc cooperates with the nios cpu to accomplish the functions of collecting ts information, detecting errors, and displaying information. the main content in this dissertation includes : ( 1 ) introducing the standard of mpeg - 2 system layer syntax and etr 290 standard about the three levels of detecting parameters ( 2 ) describing the structure and relationship of psi ; designing the hardware implement to accomplish the functions of collecting and analyzing ts information ( 3 ) analyzing and researching the three levels of detecting parameters to accomplish the partition of the hardware and software design, designing the detecting modules cooperated with the software and verifying the functions according to simulation ( 4 ) debugging and testing the design to verify it can achieve our requirements

    論文的主要內容包括: （ 1 ） mpeg - 2傳送流系統層的語法規范的介紹和dvbetr290標準中關于對碼流進行三層檢查和監測的參數的介紹; （ 2 ）描述了傳送流特殊信息之間的結構關系，介紹了用硬體方式實現碼流基本信息的提取的設計方法，並將這些信息提供給軟體進行分析處理和結果的顯示，從而實現對碼流提取和分析的功能; （ 3 ）對碼流的三層監測參數進行了分析研究，完成設計的軟硬體劃分，通過硬體設計方式完成對各個監測模塊的開發工作和時序模擬驗證，實現碼流監測功能; （ 4 ）介紹了對碼流基本信息進行提取、分析和碼流檢錯的硬體設計的調試情況和實驗驗證工作，以及最後與軟體設計部分進行聯合調試的情況
  11. At the same time, an automatic gain control and floating threshold setting intelligent detecting and processing method based on linear ccd is proposed, and the disposal and transform of ccd video signal is carried out by hardware and software

    提出了一種基於線陣ccd的自動增益控制和浮動閾值的智能信號檢測與處理方法，用硬體和軟體實現了對ccd視頻信號的進行處理和變換。
  12. Universal key management system realizes its function through software encryption algorithm and key - memory issuing functions itself through master - card. sjy49 uses key management platform by hardwares. the algorithm used in the generation, diffusion, eduction and transfer of the key is approved by the state competent department. the implementation of algorithm is functioned by the encryption equipment recognized by the state competent department

    通用密鑰管理系統採用軟體密碼演算法，密鑰存儲分發等採用母卡方式實現； sjy49銀行ic卡密鑰管理系統採用硬體化的密鑰管理平臺，密鑰的生成、分散、導出、傳輸等密鑰管理功能使用的演算法是經國家主管部門審定通過的演算法，演算法的實現使用經國家主管部門審定通過的硬體加密設備。
  13. Double - buffer is adopted to ensure gaining the speed an precision of the data acquisition

    系統採用雙緩沖技術實現連續數據採集，採用硬體中斷保證了數據採集的速度與精度。
  14. It has application in dvd and htdv and dvb - c and video transmission in network, etc. two parts the principle of video reduced on mpeg - 2 standard and the designing of encoder and debugging on encoder are primarily expatiated on in this dissertation

    本文編碼器採用fujitsu公司的mpeg - 2編碼晶元mb86390用硬體來實現視頻信號的壓縮，編成mpeg - 2碼流，可應用於dvd 、數字電視、 dvb - c及視頻的網路傳輸等。
  15. This paper focuses on the research and implementation of these six key techniques. firstly, this paper researches the international standards for compression of digital video data, analyses how to compress analog video stream to mpeg - 4 with hardware. it is also involved in the techniques of net transmit of digital video data, such as net protocol, ip multicast, rtp / rtcp and so on

    本文主要是對智能視頻監控系統關鍵技術的研究與實現，主要體現在以下幾個方面: 1 、在視頻數據的壓縮方面，研究與分析了視頻壓縮的標準以及對mpeg - 4壓縮標準做了簡單的介紹，並分析了mpeg - 4的硬體實現方式，即使用硬體編碼晶元vw2010將視頻信號轉換為mpeg - 4格式的視頻流。
  16. The author givess every functional circuit ' s designing method of intelligent nodes used reading meter collection model as object in detail, the author gives a detailed hardware designing project of collection device, based on which the author expounds designing project of intelligent nodes " applying software neuron c and singlechip program

    詳細地給出了基於lonworks技術的以抄表模塊為對象的智能節點的各功能電路的設計方法，給出具體的硬體實現；在硬體設計的基礎上，給出了採集模塊的neuronc應用軟體、單片機程序的設計及低層硬體驅動程序設計。
  17. In this paper, the hal - c conception is studied according to the project requirements, and describes the functions of the hal - c in software waveform implementation. then the issues implementing the hal - c on the specialized hardware processor are addressed, and the methods of managing the components on fpga and dsp by proxy components with the domain descriptor file and the configuration table are brought out. in the end, the validity of the proposed methods is tested

    論文以sca體系結構驗證實現項目為背景，深入研究了sca專用硬體補充規范，重點分析了硬體抽象層連接的意義以及它在波形組件開發中的作用，提出了它在dsp / fpga上實現的方法、步驟;接著從sca波形應用的角度描述了硬體抽象層連接在波形開發中的作用，給出了代理組件如何通過域描述文件和配置表管理專用硬體處理器上演算法組件的方法;最後對dsp / fpga上的硬體抽象層連接進行了驗證性測試。
  18. In such situation, controlling of the transf - orming process and synchronizing of sampled data only could be achie - ved via hardware, and data must be stored ( by using high - speed stora - ge chip ) and digital signal must be processed ( by using high - speed d - sp ) in real time simultaneously

    在這種情況下，通常只能用硬體實現轉換過程的控制和采樣數據的同步，仔細設計時序電路，同時必須採用高速存儲晶元對數據進行存儲和高速的數字信號處理器（ dsp ）完成數字信號的實時處理。
  19. The transport stream detector which is used to analyze and detect ts can accomplish the functions of collecting information, analyzing and detecting the errors of ts, displaying of information, and etc. the dissertation discusses a way of hardware implement to detect ts which is a part of design of transport stream detecting based on sopc. it uses fpga to collect and analyze program special information ( psi ) and service information ( si ), to find and store the pid numbers of every program and psi 、 si, and to detect errors of ts

    本文詳細介紹了利用硬體方式實現碼流監測的設計方案，它作為整個課題? ?基於sopc的碼流監測設計的硬體結構部分，實現了在fpga晶元內對碼流信息的採集，包括節目專用信息（ psi ） 、業務信息（ si ）的提取和分析，各套節目和psi 、 si表的pid值的查找和存儲，以及對三層碼流檢錯參數的監測。
  20. Different with traditional microprocessor which solves floating - point normalization with soft ware, the project implemented floating - point normalization with hard ware. the research focused on the architecture of microprocessor mainly

    因本課題意在實現微處理器的基本結構，並未涉及到編譯器，因此在對微處理器的浮點處理單元的規格化演算法進行深入分析的基礎上提出了用硬體實現浮點單元規格化的方法。
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