硅柵工藝 的英文怎麼說
中文拼音 [guīzhàgōngyì]
硅柵工藝
英文
silicon gate technology-
In the dissertation, the effects of the air slide - film damping on the capacitive accelerometers having different slot structures which are completely or partly etched, and fabricated by the anodic bonding between silicon and glass and bulk silicon micromachining process are researched by changing the distance between the moving structure and substrate, the thickness of the structure, the width of the completely etched slot structure, the depth of the partly etched slot structure according to the two well known air slide - film damping models
對于橫向運動的體微機械器件，其周圍空氣表現為滑膜阻尼。本文基於滑膜阻尼的兩個模型，通過改變振子與襯底的間距、振子的厚度、刻透的柵槽的寬度、沒有刻透的柵槽的深度等參數，研究了這些參數對硅?玻璃鍵合工藝製作的體硅微機械電容式傳感器阻尼特性的影響。In the paper, we introduced how to draw layout based on the standard of 0. 6 m, 5v cmos given by csc semiconductor ltd and finish the work in candence
晶元版圖的設計中採用了綠華半導體公司的0 . 6 m ， 5vcmos工藝庫，工藝基本特徵為多晶硅柵，單層金屬布線。It is believed that p - si tft will be the main type in the future panel display. among the process of manufacture p - si tft, the source and drain will have the superposition with grid for the reason of machine ’ s alignment error. the superposition will bring superposition capacitance and it will badly cut down the electric performance
在制備多晶硅tft時，由於機器的套準誤差會在柵極與源、漏極之間產生重疊部分，這樣就造成了柵源、柵漏之間的交疊電容，交疊電容的存在嚴重影響了多晶硅tft的性能，而利用自對準工藝制備的多晶硅tft則避免了交疊電容的產生。Applying silicon gate technology, the chip has a lower value in power consumption than the products made by aluminum gate technology
由於採用硅柵工藝，該晶元比市場上曾經流行過的鋁柵產品功耗更低。Wirings of the poly layer are always utilized under the silicon grid technics. to control the macro - cell signal delay and improve signal integrality, the crossing among different nets must be averagely distributed to reduce the number of layer permutation. the metal layer wirings should be maximized and the length of poly layer wiring in each net should be minimized
硅柵工藝晶體管級布線利用多晶層走線，為了控制宏單元時延性能及改善信號完整性形態，關鍵是不同線網間交叉的均衡分配以減少走線的換層次數，最大化金屬層走線以及每一線網多晶層走線長度的有效控制。By studying and using conventional 1c process in combination with electron beam lithography ( ebl ), reactive ion etching ( rie ) and lift - off process, several efficient results are produced : semiconductor and metal nano - structures are fabricated ; the matching problem of photolithography and electron beam lithography is well solved ; the process efficiency is improved ; the process is offered for the controlled fabrication of nano - structures by repetitious process testing ; several nano - structures such as si quantum wires, si quantum dots, double quantum dot structures and tri - wire metal gate are firstly fabricated by using ebl and rie processes
研究利用常規的硅集成電路工藝技術結合電子束光刻，反應離子刻蝕和剝離等技術制備半導體和金屬納米結構，很好地解決了普通光刻與電子束光刻的匹配問題，提高了加工效率，經過多次的工藝實驗，摸索出一套制備納米結構的工藝方法，首次用電子束光刻，反應離子刻蝕和剝離等技術制備出了多種納米結構（硅量子線、量子點，雙量子點和三叉指狀的金屬柵結構） 。Finally the method of preparation of p - si tft and some useful dates were given. the dissertation includes seven chapters. the first chapter introduces the development of tft ; the second chapter introduces the principle of tft and its structure ; the third chapter provides the reason of superposition capacitance between s, d and gate ; the fourth chapter introduce the deposition and test method of sinx ; the fifth chapter introduces the fabrication of p - si ; the sixth chapter studies the fabrication techniques of p - si tft and some parameters ; the seventh chapter is a conclusion of the research
本文一共分為七章:第一章介紹了本論文的研究背景、研究意義、主要工作以及國內外的研究進展;第二章介紹了tft的結構和工作原理;第三章介紹了柵極與源、漏極之間疊加電容產生的原因和自對準工藝;第四章介紹了氮化硅的制備方法和測試方法;第五章介紹了多晶硅tft有源層的制備方法並對各種晶化機理做了介紹;第六章主要對利用自對準工藝制備tft的工藝進行研究，並對制備出來的樣品進行了測試;第七章對全文進行總結。分享友人