硬體實現 的英文怎麼說
中文拼音 [yìngtǐshíxiàn]
硬體實現
英文
hardware implementation-
New s - boxes for hardware implementation of aes
適合aes演算法硬體實現的新s盒On the basis of the research of former graduates, we design the hardware & software of digital boxcar by employing the high - speed ad fpga chip and the usb protocol controller chip, and we realized the high - speed sampling, digital adding, high - speed storage, data transmission and interface circuits of pc successfully
根據實驗室前幾屆研究生的積累，前人研究方案的基礎上，利用ad晶元、 fpga晶元和usb協議控制晶元重新設計了boxcar的硬體實現電路和相應的檢測軟體。Because of the quickness in calculating and briefness in algorithm, mm will be a preferable approach to nonlinear speech signal processing
由於數學形態學并行快速、易於硬體實現，很可能成為一種新的非線性語音處理方法。The results of experiment tell it is an effective method of share current. a strategy of synchronization control, which combines competition coequality and priority, is mentioned in the paper and uses digital phase - lock loop to track synchronization signal
在同步控制上，應用了「優先與搶占」的方式產生同步信號，純硬體實現，簡單可靠；使用了成熟的數字鎖相環來跟蹤同步信號。According to the research, the major work done is as following : < 1 > analyzes the symmetric - key encryption algorithm des and dissymmetric - key encryption algorithm rsa, and makes them easy to realize in hardware. < 2 > according to the algorithms and the thought of reconfigurable computing, the dissertation accomplishes the design of 64 - bit des system architecture and the design of 256 - bit ~ 1024 - bit rsa system architecture. < 3 > using the top - down high level design methodology and the hdl language, accomplishes the description of the des / rsa designs, the simulation and the synthesis
本論文主要的研究工作： < 1 >對現有的對稱加密演算法des演算法和非對稱加密演算法rsa演算法進行分析，使其易用硬體實現； < 2 >基於可重構思想和特點，完成64位des演算法和256位1024位模長rsa演算法的可重構硬體的設計； < 3 >採用自頂向下的設計方法，利用hdl語言對des / rsa設計進行功能描述，並完成軟體模擬，綜合和布線； < 4 >在可重構計算驗證平臺上進行演算法驗證，並對設計的可重構和設計的進一步優化進行討論。This thesis tries to update the cmdsr system to achieve the characters below : real - time, better robust, higher recognition rate, non - special - man. considering the disadvantages of traditional improved spectrum subtraction speech enhancement, this thesis proposes the theory of fuzzy spectrum subtraction based on the fuzzy theory and improved spectrum subtraction speech enhancement ; as for the difficulties of detecting the endpoint of speech signal, the thesis gives the table of initial and the improved parameters, with which we can confirm the endpoints of mandarin digit speech ; the thesis puts forward two - level digit real - time speech recognition system, the first level is based on discrete hidden markov model which is linear predictive coding cepstrum ( lpcc ) and difference linear predictive coding cepstrum ( dlpcc ), the second level is based on formant parameters ; as for the realization of hardware, the thesis depicts the realization of every part of cmdsr based on the tms320vc5402 in detail ; as for the development of software, the thesis gives the software design flow chart of cmdsr, simulates the basic theory with matlab language and gives the simulation results
針對傳統的「改進譜相減法語音增強」參數設定單一、環境適應能力差的缺點，提出了一種利用模糊理論和「改進的譜相減法」結合的「模糊譜相減法語音增強」 ;針對語音信號端點檢測困難的特點，通過matlab模擬試驗，給出了能夠準確確定數碼語音端點的初始和改進參數表;提出了利用基於線性預測編碼倒譜參數和差分線性預測編碼倒譜參數相結合的離散隱含馬爾可夫模型進行第一級識別、利用共振峰參數進行第二級識別的兩級漢語數碼語音識別系統，在保證系統實時性的同時，實現連接漢語數碼語音識別系統識別率的提高;在硬體實現上，詳細闡述了基於tms320vc5402的連接漢語數碼語音識別系統各部分硬體設計;在軟體開發上，給出了連接漢語數碼語音識別的軟體設計各部分的流程圖，並對各部分進行了matlab模擬，並給出了模擬結果。8 abdallah a e, hawkins j. formal behavioural synthesis of handel - c parallel hardware implementation for functional specifications. in proc
因此，在建議的方法學中，也建議將handel - c作為最終的可重新配置的硬體實現平臺。Eventually, the digital correlator of the modificatory structure is designed and realized by fpga, and it manifests very high and reliable correlative performance
最後用fpga晶元設計並硬體實現了修正結構的數字相關器，這種結構的數字相關器具有很好的工作性能。In addition, many other problems also exist in hardware neural network, including error problem, learning mode, parallel architecture, and also neural network inner linking problem, hidden layer and the realization of the multiplicator and etc. for instance, error problem : hardware neural network employs the limited precision, and will inevitably bring limited precision error
另外，硬體實現神經網路還存在誤差問題，學習方式，并行結構等方面的問題，還有神經網路內部的連接問題，隱層及乘法器的實現等等。如誤差問題，硬體實現神經網路使用的是有限精度，不可避免的會產生有限精度誤差，選取合適的精度，才能既適合空間的要求，又避免對網路的實現產生一定的影響。Signal channel is composed of photodetection preamplifier and filter circuit, reference channel and correlation demodulator are realized by labview
信號通道由硬體實現，包括光電探測前置放大電路及濾波電路;參考通道及相關解調器部分則利用labview軟體編程實現。In the thesis, a good performance is gained with implement four 256 state machines by making good use of residuary block ram in fpga chip. in present dissertation, ts sync flag is got rapid - extract by software and hardware cooperation and whether packet length is 188 or 204 bytes also is distinguished
在硬體實現的過程中，對傳統da演算法進行了深入研究，充分利用fpga片內剩餘ram塊，實現4個256狀態的狀態機，採用軟硬體協作的方法快速提取同步位元組，自動區分包類型是188位元組長還是204位元組長。Research of hardware implementation in fft ratl - time signal processor
實時信號處理器的硬體實現研究Survey for hardware realization of ant colony algorithm
蟻群演算法硬體實現的研究進展Secondly, the paper describe the principle of atm network, and the function of ' sar " ( segmentation and reassembly ) and the format of packet aal5, and introduce the basic idea of ipoa, and the design project and implementing of the control chip. later, the paper introduce the logic function and operational principle of packet buffer control chip and prove the feasibity and correctness of the arithmetic. at last the paper introduce crc - 32 arithmetic based on look up and implement it with hardware
接著詳細論述了核心路由器atm網路實現的原理，包括「 sar 」 （ segmentationandreassembly ）功能和aal5報文的格式， ipoa基本思想，以及控制晶元的設計方案和實現途徑等。然後又論述報文緩存區控制晶元的工作原理和邏輯功能等，並對演算法的可行性，正確性等進行論證。最後介紹了一種基於查表的crc - 32演算法的原理及其硬體實現。The current researches include how to cut down the computation complexity, how to reduce the average coding bit rate, how to improve the quality of reconstructed image, and which algorithm to be suitable to vlsi implementation
在該技術中，減少運算復雜度、降低平均編碼比特率、提高恢復圖像的質量和便於硬體實現等方面是當前研究的主要方向。The hardware / software co - synthesis determines the hardware and software a ] location and function mapping. hardware / software co - synthesis is a key problem of hardware / software codesign
軟硬體協同綜合決定系統功能在軟硬體實現結構上的分配，是軟硬體協同設計的核心問題。After the investigation of the general technology of hardware implementation, how to implement the kasumi algorithm using field programmable gate array ( fpga ) device is discussed in detail, and the author develops the cipher chip of kasumi algorithm, the kasumi cipher card based on 32 - bits pci bus, the wdm device driver that used in windows2000 / xp, and the software to demostrate encrypting data link. finally, an application demostration is constructed with all the above implementation
在此硬體實現的結果晶元基礎上，設計了32位的基於pci總線的kasumi加密卡，編寫了windows2000 xp下的windows驅動程序模型（ wdm ）驅動程序和鏈路加密應用程序，由此構成一個應用演示系統，作為研製結果的應用評估，為進一步進行第三代移動通信系統相關安全技術研究和開發提供了基礎條件。For its characteristic of parallel logic and dispersed state, ca can be realized easily in hardware
元胞自動機的并行邏輯特性以及離散狀態等特性，使其易於硬體實現。Based on statistic property of all sub - bands coefficients, this paper gives a lossless image coding scheme including dpgm, huffman coding and run length coding. this scheme reduces the calculating complexity and works highly efficiently
針對圖像整數小波分解后的各子帶系數的統計特性，提出結合dpcm ， huffman及遊程編碼的無損圖像編碼方法，該方法運算簡潔，速度快，易於硬體實現。In this paper, the method of digital evolvable hardware is studied based on the dynamical reconfiguration of field programmable gate array ( fpga ). in the paper, firstly, the basic conception and theory of ehw are roundly introduced and the structure characters of ehw chip are analyzed. secondly, the thought of standard evolutionary algorithm is discussed and the flow of improved evolutionary algorithms is analyzed
本文首先較全面地介紹了硬體演化技術的基本概念和原理，分析了演化硬體晶元的結構特點；其次，討論了標準演化演算法的思想並對改進型演化演算法的流程進行了分析；然後著重分析了演化硬體實現中的關鍵技術，對其實現方案進行了深入的研究，文中分別採用外部演化和內部演化兩種方式對不同的應用電路進行了演化。分享友人