硬體流水線 的英文怎麼說

中文拼音 [yìngtǐliúshuǐxiàn]
硬體流水線 英文
hardware pipeline
  • 硬 : 形容詞1 （堅硬） hard; stiff; tough 2 （剛強; 堅定; 強硬） strong; firm; tough; obstinate 3 （勉...
  • 體 : 體構詞成分。
  • 流 : Ⅰ動1 （液體移動; 流動） flow 2 （移動不定） drift; move; wander 3 （流傳; 傳播） spread 4 （向壞...
  • 水 : 名詞1 （由兩個氫原子和一個氧原子結合而成的液體） water 2 （河流） river 3 （指江、河、湖、海、洋...
  • 線 : 名詞1 （用絲、棉、金屬等製成的細長的東西） thread; string; wire 2 [數學] （一個點任意移動所構成的...
  • 硬體 : hardware
  • 流水 : 1 （流動的水） running water; stream2 （舊時指商店的銷貨額） turnover （in business）流水搬運作用...
  1. On the demand of application and according to the soluhons menhoned above, a method of displacement waiting auto - sy ' nchronizing is put forward, which is based on match filters. at the end a complete and speeflc set of hardware circuits and software programs which haplements the scheme, is also presented in the ancle. the synchronization system was tested in the pool and in the shallow wate near m port, the result of the test shows that its performance is satisfactory

    論文著重介紹實現了跳頻通信系統同步的一般方法，並詳細分析和對比跳頻同步系統的捕獲方案，在此基礎上，提出了一個基於匹配濾波器的位移等待式自同步方案，設計、完成並給出了詳細硬體連線電路圖、軟體程序流程圖和部分程序清單，該自同步方法在實驗室水池實驗取得良好的效果，並在廈門港海域進行了現場實驗測試，具有較低的誤碼率和一定的檢測概率，結果令人滿意。
  2. The methods for solving these problems are put forword as follows : the method of airphoto scale rangs from 1 / 4 to 1 / 6 of map scale ; a flight line uses belt method ; the optional time intervals of airphoto taking are from may to june and from august to october in one year ; when the contrast at the site is small, or the visibility is rather low and needs to enchance the contrast, the hardening agent should be prepared to process the film

    並提出了解決問題的方法：山區航空攝影合理的攝影比例尺應是成圖比例尺的1 / 4 ~ 1 / 6 ；對于山區窄而長，且為線狀走勢的河流宜採用帶狀航線設計方法設計；山區流域水分充足能見度不好，惟每年5 - 6月和8 - 10月是航空攝影的最佳季節；當地面物體反差小或能見度不好而需要特別提高反差時應配製較硬性藥水沖洗等。
  3. This project focus on r & d of remote information transfer between some device, especially in the water - quality monitoring system. after learning the architecture of the popular pstn dial - up network. vpn broadband network and gsm wireless network, a new solution for remote communication was proposed. under this idea frame a communication hardware platform and software was developed

    本課題主要針對環境水質在線監控系統中的信息傳輸問題，對遠距離設備之間的信息傳輸方式及發展進行了研究，結合目前流行的pstn撥號上網方式、 vpn組網技術和gsm無線數字通訊技術，提出了一種新型的遠程設備之間信息傳輸與互聯的方案，並按照這個思路搭建出系統所需的硬體平臺，設計出實現這個方案的應用程序。
  4. The hardware has two input channels of high - speed analog signal, with the signal amplitude of 0 - 5v, the conversion precision of 12bits, and the maximum sampling rate of 400ksps. this system includes 4 dsps ( adsp 2181 ), which can be arranged as a pipe line processing array. many algorithms can be realized in this system

    系統硬體有兩路模擬數據採集通道，模擬信號輸入范圍為0 ? 5v ，轉換精度為12位，最高采樣率400ksps ；系統包含4片dsp （ adsp2181 ）構成的流水線型的處理陣列，可用於實現各種演算法；系統的控制邏輯由fpga完成。
  5. The inversionless bm algorithm in rs decoder is implemented with serial mode, which avoids the inversion computation and only needs 3 finite - field multipliers. thus, the complexity of hardware implementation has been mostly reduced. a 3 - level pipe - line processing architecture is also used in the hardware and the coding circuit in rs coder is optimized by using the characteristics of the finite - field constant multiplier

    Rs解碼器的設計採用無逆bm演算法，並利用串列方式來實現，不僅避免了求逆運算，而且只需用3個有限域乘法器就可以實現，大大的降低了硬體實現的復雜度，並且因為在硬體實現上，採用了3級流水線（ pipe - line ）的處理結構。
  6. This paper introduces the history of the gpu firstly, and then it analyses the pipeline architecture of gpu. finally, it introduces several types of program languages of gpu

    本文首先介紹了可編程圖形硬體的發展，然後分析了它的流水線結構，最後介紹了幾種最新的編程語言。
  7. On the basis of designing the serial structure of mq encoder, parallel structure of mq encoder is designed using pipelining technique and the coding rate is approximately 1bit / cycle

    為了得到更高速率的mq編碼器，採用流水線結構設計了并行的mq編碼器。模擬結果表明mq編碼器的編碼吞吐量明顯提高，達到了硬體規模和編碼效率的平衡。
  8. Considering that the time of image preprocessing is the key fact affecting the performance of real time, it designs hardware circuits for median filtering and edge detection. the pipelined and parallel processing methods are used in circuit design to raise processing speed and save hardware resource

    針對影響系統實時性最大的圖像預處理部分，在fpga設計中，實現了預處理的中值濾波和邊緣檢測硬體電路，將流水線處理技術和并行處理等技術應用到電路設計中，提高了處理速度，節省了硬體開銷。
  9. For the real time performance need of the low speed speech compress algorithm and the asic implement of the transfer process between programs, the design is put forward in the paper, in which state registers control the cross access between operator and memory, register windows are used for the parameters transfer, and the technique of hardware controlling is used to avoid pipeline conflict, so that the main problems of the transfer process in tr600 are solved effectively

    摘要針對低速率語音壓縮演算法對處理器系統實時處理復雜運算的性能要求，就程序調用過程的asic實現問題進行了對比與分析，進而提出了用層次狀態寄存器控制存取運算元對存儲體交叉訪問的方法，並結合運用寄存器窗口傳遞參數的功能，以及利用空指令硬布線處理流水線沖突的方法，有效地解決了tr600晶元中調用過程存在的主要問題。
  10. A raw ( read after write ) dependency loop model is developed in this paper to analyze the raw hazards of register operands in complex pipeline. based on this model, a " dynamic " data forwarding policy is suggested to reduce the pipeline stalls caused by data raw hazards. theoretical analysis and practical experiments both show that the average cpi increment caused by data raw hazards can be reduced effectively by the dynamic data forwarding strategy

    對于單發射結構的處理器，降低cpi值的根本途徑在於通過各種軟硬體技術減少流水線的停頓，本文構造了一個raw相關環路模型用於分析流水線中寄存器操作數的raw競爭現象，並提出了一種「動態」數據旁路優化策略，可以最大程度地減少復雜流水線中因數據的raw競爭而導致的互鎖停頓，理論分析和實測結果充分表明「動態」數據旁路機構可以有效地降低流水線因raw互鎖導致的平均cpi增量。
  11. Introducing same ideas on future design high performance branch prediction, including manufacture technology, depth of pipeline, micro - architecture and so on. 5, research selective dual path execution architecture. introducing hardware mechanism of multi - path execution, including branch forking strategy and branch prediction confidence

    4 、分析了高性能轉移預測設計中的問題；對未來設計高性能轉移預測器所面臨的問題以及解決這些問題的可能的辦法，包括製造工藝、流水線的深度和處理器的微體系結構等5 、對選擇雙路徑系統結構的分析；介紹選擇性雙路徑執行中的硬體機制?轉移置信度評估和選擇轉移策略。
  12. This dissertation combines hardware descriptive language, production line transfer technology, ping - pang memory technology and fpga wiring optimization technology to implement data branch and treating

    本文綜合運用硬體描述語言、流水線傳輸技術、乒乓存儲技術、 fpga布線優化技術實現了採集卡的數據分流及處理。
  13. In system hardware design, data pipeline of the separation of reading and writing, which aims at data memory control - flow analysis in raid and reduces the resource ' s expanse of memory system, is established

    在系統硬體設計中，針對數據在raid中的存儲控制流程，建立了讀寫分離的數據流水線，減少存儲系統的資源開銷。
  14. In addition, both the series - parallel connection and parallel pipeline for the circuit structure are availed to cut down hardware area and improve processing speed of the system

    同時，為保證系統的實時處理速度和降低硬體成本，在演算法的vlsi實現時採用串並結合和并行流水線等設計。
  15. The glass shell of the kinescope is an important part of the computer screen. in order to identify, classify and count the different kinds of glass - shell on product line. it researches the methods of measurement and data management about glass shell at two positions

    顯像管玻殼是計算機顯示器、電視機及監視器的重要組成部分，針對玻殼生產企業生產流水線上的玻殼產品，本文研究開發了基於機器視覺的在線玻殼分類計數的軟硬體系統。
  16. And hardware / software coverification is carried out to guarantee the correctness of design. in the design of hardware of memory system, according to the system specification, we select the appropriate memory capacity, sram block, associativity and the placement of cache in the pipeline

    在存儲系統的硬體設計中，始終以性能指標作為依據，克服了存儲器容量、庫單元規格選擇、聯合度的選擇和cache在流水線中的位置選擇等困難，設計出了符合指標要求的指令存儲系統。
  17. Pipelining and parallel technology, accompanying with fast fifo as cache memory, instead of direct program operation, are adopted in the scheme and increase the transmitting speed dramatically ; fpga ( field programmable gate array ) is applied to realize the complex control logic of the system and makes it integrative, flexible and fast ; 386ex based embedded system, along with vxworks real - time operating system is introduced to substitute the microcontroller based system to simplify the hardware design and enhance the overall performance of ssr, and will make the system more easier to be applied to the projects in the future

    該設計方案採用了流水線和并行技術，配以快速fifo緩存的方式取代了直接對flash進行編程的方式，極大地提高了閃存晶元存儲數據的速率；採用fpga技術實現系統的主要控制邏輯，集成度高、靈活性好、速度快；採用基於386ex的嵌入式系統及基於vxworks的嵌入式實時操作系統，取代單片機系統及其編程，提高了系統的整體性能，減輕了硬體設計的負擔，且使系統研發的延續性好。
  18. We can ration analyze and estimate hardware configure chosen in design such as machine tool, the capacity of buffer, the route of transport system etc, and personnel deployment of product line. we can forecast the produce cycle of product, analyze and forecast produce capacity of work - flow, simulate all kinds of predictable or random malfunction, finding bottleneck of system etc. we can also forecast the capability of work - flow under different scheduling strategy

    通過對流水線的模擬，我們可以對各種設計方案進行評估，可以定量分析與評價設計中所確定的硬體配置（如機床、緩沖庫容量、運輸系統路徑等）及生產線人員配備情況，預測產品生產周期，分析與預測生產線的生產能力，模擬各種可預見的或隨機的故障，發現系統瓶頸等。
  19. Secondly, this paper analyses several kind of np, based on this work, author summarizes the characteristic of np, and introduces the new technology that used by np. finally, author chooses the np3400 network processor, which has a fabric and 32 - bit risc processor core and is the product of amcc company, to be the reference design, based on the pipeline of armp, scheme out the pipeline of risc processor core that compatible with np3400

    接著，在大量考察了多種商用網路處理器的結構的基礎上，本文初步分析了網路處理器的硬體結構特點，並對網路處理器中使用的新技術進行了討論，在此基礎上，本文選取了美國amcc公司推出的一款具有交換架構和32位risc處理內核的網路處理器np3400作為主要研究對象，以armp的流水線為基礎，設計了risc處理核的流水線。
  20. Hi the hardware pat, we design the units of high - speed cache and pipeline, which are absent in other similar products ( in today ' s market )

    在硬體開發中，論述了目前國內市場上同類產品所沒有的高速緩存cache和流水線等部件的研究與設計。
分享友人
分享到 Line

分享到臉書