硬體解碼器 的英文怎麼說

中文拼音 [yìngtǐjiěmǎqì]
硬體解碼器 英文
hardware profile
  • 硬 : 形容詞1 （堅硬） hard; stiff; tough 2 （剛強; 堅定; 強硬） strong; firm; tough; obstinate 3 （勉...
  • 體 : 體構詞成分。
  • 解 : 解動詞（解送） send under guard
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 硬體 : hardware
  • 解碼器 : codec
  • 解碼 : decoding; decipher; decode
  1. The hardware of the ip phone codec to be designed is based on the fixed point digital signal processor ( ti ' s tms320vc5410 ) while the compression and decompression core in the software of dsp is based on the itu - t vg. 729a. ip phone codec carryout the task of collecting / playing - back. coding / decoding of speech signal and communication with embedded cpu. etc

    該語音編解碼器的硬體基於tms320vc5410 ，編解碼演算法遵循itu - tg . 729a協議，能夠實現語音信號的採集/回放、編碼/解碼以及同嵌入式cpu通信等功能，在8kbit / s的碼率下能夠提供獲得良好的語音質量。
  2. It uses adi company ’ s blackfin 533 as a cpu to realize vedio real - time decoding, and uses pc to realize vedio real - time coding. then the solution of the vedio command system in sse is presented

    文章採用adi公司的blackfin533來作為核心硬體處理器來實現視頻實時解碼，採用pc機實現視頻實時編碼，給出了單兵作戰視頻指揮系統解決方案。
  3. With argumentation and comparing the difficulty of developing in different ways, in multimedia communication the terminal make up with mpeg - 4 encoder and decoder based on vw2010 chip, main controller based on x86 core and pc compatible stpc soc chip, ethernet adapter based on rtl8139. and this hardware platform can run linux operation system. the following works are done by auther. 1. participate in designing the project of multimedia terminal

    經過論證和比較，權衡了開發難度和系統性能，在多媒體視頻會議終端設計中採用了基於x86內核片上系統晶元stpc的主控制器模塊，基於vw2010晶元的mpeg - 4音視頻編解碼器模塊，基於rtl8139晶元的10m / 100m以太網適配器模塊的硬體架構，主控制模塊運行linux操作系統，作為多媒體終端的軟體運行環境及軟體開發環境。
  4. In this paper, a new architecture of hardware decoder based on the modified euclidean algorithm ( mea ) is provided, and it is called the fprme ( fully - pipelined recursive modified euclidean ) decoder

    本文基於修正的歐幾里德演算法（ mea ）設計了一種新的硬體解碼器實現結構，稱其為fprme （ fully - pipelinedrecursivemodifiedeuclidean ）解碼器。
  5. The inversionless bm algorithm in rs decoder is implemented with serial mode, which avoids the inversion computation and only needs 3 finite - field multipliers. thus, the complexity of hardware implementation has been mostly reduced. a 3 - level pipe - line processing architecture is also used in the hardware and the coding circuit in rs coder is optimized by using the characteristics of the finite - field constant multiplier

    Rs解碼器的設計採用無逆bm演算法，並利用串列方式來實現，不僅避免了求逆運算，而且只需用3個有限域乘法器就可以實現，大大的降低了硬體實現的復雜度，並且因為在硬體實現上，採用了3級流水線（ pipe - line ）的處理結構。
  6. Comparing and analyzing the synchronous control strategy, which brings up the new method to control the double un - symmetry jars proceed synchronously with the combination of proportional valve and servo valve, which forms closed loop control ; basing on the above methods, models are made to get mathematics models of position control system and to analyze system model theoretically by using pid controller, we can realize regulating parameters, minimizing synchronous errors and enhancing the dynamic performances ; the simulink tool box in matlab software is used to imitate the system according to the model, which not only makes the result visual and easy to adjust the parameters in interactive way but also lets us understand the effects of different parameters and optimizes the dynamic properties. the theory of plc control in dshp is discussed after advanced understanding of the system movements. hardware design and general regulation are given on the base of siemens company products s7 - 200 plc

    本文根據大量的國內外文獻，對研配液壓機的工作原理及設計結構進行了簡介；對位置同步的控制方法進行了比較分析，提出比例閥和伺服閥復合控制的閉環結構來對非對稱雙缸進行同步控制電液比例同步控制方案；在此基礎上著重對比例閥控非對稱缸建模，最後得到位置控制系統的總體數學模型，從理論上對同步系統動態特性進行了分析，並用pid控制器進行參數整定，減小雙缸同步誤差、提高系統的動態響應性能；其中控制性能的分析藉助于matlab軟體中的simulink工具箱，由已建立的數學模型形成模擬模型，得到可視化的模擬結果，從而利於交互方式下調整參數，了解不同的參數對系統的影響，優化同步系統的動態性能；在深入了解系統的動作特性后，對plc控制研配液壓機的原理進行了探討，針對siemens公司s7 ? 200型plc給出了硬體設計的總體規劃，編制出研配液壓機動作控製程序，在編程中著重研究位移傳感器與plc的通訊、雙缸同步運行的pid控制在plc上的實現及bcd碼撥盤輸入程序的植入問題。
  7. Firstly, the system is divided into many modules according to different point of view ; secondly, to the hardware equipment - vidicon, lenses, revolver, shield and decode device, their principle of work has been explained ; thirdly, according to image identification experience and other indexes of the system, the focus of the lenses and relative aperture are calculated, and the type of the camera is confirmed, at the same time, the energy of infrared lamp is also computed in the thesis ; at the same time, synthesis control box is devised

    首先，按照角度的不同，將系統劃分成許多模塊。其次，對硬體設備? ?攝像機，鏡頭，雲臺，防護罩，解碼器等的工作原理進行了闡述，再次，以人的成像辨認的經驗判據為依據，結合系統的其它指標，設計計算出鏡頭的焦距f 、相對孔徑d ，同時確定攝像機的型號，並計算出紅外燈光源。最後，對綜合控制箱進行設計，指出了設計的意義，實現的功能，並附上了綜合控制箱的外形圖。
  8. Based on the realization of the encoder / decoders, this scheme aims at the highest rate downstream frame, and has realized the parallel fec circuit and scrambler complying with the protocols and maken a simulation. the fprme decoder is advanced in the world. the parallel fec circuit completely conforms to the itu - t protocols, and has important practical value

    在rs （ 255 ， 239 ）硬體編碼器/解碼器實現的基礎上，本文按照gpon協議要求，針對gpon中最高速率2 . 488gbps的下行幀，通過設計復雜的操作時序，實現了符合協議規定的32位并行fec編解碼和解擾碼電路，並作了模擬。
  9. Therefore we have built up the whole hardware platform and fpga debugging environment, while optimizing the mp3 decoding performance by fosusing on improving the hardware processor

    為此我們設計了完整硬體平臺以及fpga調試環境，同時我們也針對硬體處理器對mp3解碼程序進行了優化。
  10. Applying singlechip in the receiving system, this method can make the best of singlechip ' s resource of software and hardware and provide a reasonable and cheap resolving project for wireless remote control

    在發射系統中採用十進制至8421碼編碼器實現對開關按鍵編址，從而對受控電路進行選擇控制；在接收控制系統中引入單片機，通過充分利用其軟、硬體資源，為無線電遙控提供了合理、廉價的解決方案。
  11. The line code is very efficient for bit synchronization in the communication systems and it is useful to choose the appropriate line code. the dissertation introduces the advantages of the manchester code, then studies the way to realize the encoding and decoding of the manchester code, and introduces the process of the joint - debugging on the whole system. the contents of this dissertation are as follows : 1

    本文首先討論了線路編碼與實現通信中位同步的關系，以此為出發點，討論了曼徹斯特碼作為一種線路碼于其他碼型的相對優勢，而後研究了編解碼器實現方案中的幾種待選方案，並對幾種方案做了對比論述后，設計了合適的方案，接著詳細研究了曼徹斯特碼編解碼器的硬體實現並進行了模擬。
  12. In this paper, we give a detail discussion on the key technology, including software and hardware designing of g. 729a multi - channel speech codec realtime implemention on a simple dsp processor - tms320c6202. in combination with the requirements of a military communication network, the atm adaptation solution of g. 729 coder bit stream is analyzed. a kind of new atm adaptation technology - aal2 is introduced. the analyse and research of aal2 are provided

    本文詳細討論了多路g . 729a語音編解碼器在一片dsp處理器tms320c6202上實時實現的軟硬體設計和關鍵技術。結合某軍事通信網設備的需要，進而對g . 729語音編碼的碼流的atm適配方案進行了分析。提出了用一種新的atm適配技術- - aal2進行適配的方案。
  13. A high - performance hardware architecture of cabac decoder

    解碼器硬體結構設計
  14. 3. generating the schematic and the pcb layout, debugging the software and hardware. 4

    3 .設計編解碼器的原理圖及電路板，完成單板的軟硬體調試。
  15. The survey of vidio compressed coding is introduced in this paper at first. then the vidio compressed method based on transform coding and the content of mpeg - 2 standard are presented. the hardware realization method of mpeg - 2 vidio compressed decoder is given in detail

    本文首先介紹視頻壓縮編碼發展的概況；然後介紹基於變換編碼的視頻壓縮方法，並簡要闡述mpeg - 2標準的內容；隨后給出了一種基於專用晶元的mpeg - 2視頻壓縮編解碼器硬體實現方法。
  16. The task is based on st ’ s sdtv channel decoder solution with a highly integrated single - chip fully digital qam demodulation stv0297. chapter 1 introduced the interrelated background of this item ; chapter 2 introduced the coding and decoding theory about channel ; chapter 3 described the hardware structure, the function, the realizing principle and the method of the pcb design ; the scheme and flow chart of software design are also described in detail in chapter 4 ; chapter 5 described the testing and analyzed the result ; at last, chapter 6 presented the summing - up of this dissertation

    第一章介紹了本項目的相關背景知識;第二章簡單描述了通道編解碼原理;第三章系統地介紹了標準清晰度數字電視機頂盒通道解碼器的硬體構成、功能和實現原理，並介紹了電路板的設計方法;第四章對通道解碼的軟體設計方案和實現流程也做了比較詳細的闡述;第五章給出了測試結果並對其進行了分析;第六章對本論文進行了總結。
  17. Thirdly, this dissertation gives a synchronization algorithm of double work - stations " playing out based on digital reference information

    同時，該演算法也對mpeg硬體解碼器及其他多路復用格式的視音頻解壓具有借鑒價值。
  18. During the process of voice terminal design, the author firstly presents its hardware structure, including the coding and encoding module of ip, the interface to former access network equipment and etc, and then the author illustrates in detail the software realization of g723. 1 & g711 coder and encoder, then introduces how to realize the application of rtp / rtcp protocol in h. 323 gateway by openh323, including the design of the process and the realization of the data package format and partial code

    在語音終端設計中，首先提出了其硬體構架，包括ip語音編解碼模塊，與原接入網設備的介面等；然後重點討論了g . 723 . 1和g . 711編解碼器的軟體實現。在h . 323網關模塊中，首先討論了ip電話網關的系統架構；接下來介紹了openh323軟體開發包，並詳細介紹了利用openh323實現rtp / rtcp協議在h . 323網關中的應用，包括流程設計，數據包格式和部分代碼實現。
  19. The paper mainly specify decoding of sti5512 and design of pci card, and seriously study the digital tv system and pci2. 20 specification

    本論文主要講述sti5512解碼器的解碼和pci介面硬體設計，並認真研究了數字電視系統和pci2 . 20規范。
  20. Hardware implementation for the all - erasure rs decoder is proposed, including the finite field arithmetic operation units

    本文並提出純粹抹除式里德所羅門解碼器的硬體實現，包括有限體中的算數運算模組。
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