硬體驗證 的英文怎麼說

中文拼音 [yìngtǐyànzhèng]
硬體驗證 英文
hardware verification
  • 硬 : 形容詞1 （堅硬） hard; stiff; tough 2 （剛強; 堅定; 強硬） strong; firm; tough; obstinate 3 （勉...
  • 體 : 體構詞成分。
  • 驗 : 動詞1. （察看; 查考） examine; check; test 2. （產生預期的效果） prove effective; produce the expected result
  • 證 : Ⅰ動詞（證明） prove; verify; demonstrate Ⅱ名詞1 （證據） evidence; proof; testimony; witness 2 （...
  • 硬體 : hardware
  • 驗證 : test and verify; checking; proving; testing; confirmation; [數學] corroboration; inspection; veri...
  1. Because it ’ s hard to get radiation - harden hardware overseas, so the software fault tolerance techniques are significant for our national space enterprise. the computer platform of 863 plan project ” micro intelligent free - flying space robotic system ” consists of cots component. the orbit and the radiation environment of the robot are similar to ones of the argos satellite, and the system is required to have high reliability. therefore it ’ s necessary to applied the software fault tolerance techniques into the system to improve the anti - radiation capability after the techniques been verified valid

    因為我國很難從國外獲得輻射加固的硬體，所以，這項軟體容錯技術對我國航天事業的發展具有較大意義。 863計劃項目「小型智能飛行機器人系統」所用的計算機平臺採用商用器件，其衛星的運行軌道與argos衛星軌道近似，面臨的輻射環境與argos衛星相似，要求具有高可靠性。因此，小型智能飛行機器人系統有必要在驗證sihft技術有效的基礎上，應用軟體容錯技術，提高其空間抗輻射能力。
  2. According to the research, the major work done is as following : < 1 > analyzes the symmetric - key encryption algorithm des and dissymmetric - key encryption algorithm rsa, and makes them easy to realize in hardware. < 2 > according to the algorithms and the thought of reconfigurable computing, the dissertation accomplishes the design of 64 - bit des system architecture and the design of 256 - bit ~ 1024 - bit rsa system architecture. < 3 > using the top - down high level design methodology and the hdl language, accomplishes the description of the des / rsa designs, the simulation and the synthesis

    本論文主要的研究工作： < 1 >對現有的對稱加密演算法des演算法和非對稱加密演算法rsa演算法進行分析，使其易用硬體實現； < 2 >基於可重構思想和特點，完成64位des演算法和256位1024位模長rsa演算法的可重構硬體的設計； < 3 >採用自頂向下的設計方法，利用hdl語言對des / rsa設計進行功能描述，並完成軟體模擬，綜合和布線； < 4 >在可重構計算驗證平臺上進行演算法驗證，並對設計的可重構和設計的進一步優化進行討論。
  3. In all kinds of complicated network, oriented linking and unlinking, communication frequency resource is strained, and bandwith to transmitting audio frequency signal is too restricted, complicated and fluky, while audio frequency data exponential have been increased in the last several years. under the circumstances, based on the research of predecessor, this paper studies wavelet analysis ' s maths gist and practices significance on signal process, and puts forward a optimized wavelet package condensation arithmetic to process audio frequency data, which gives attention to coding efficiency, multirate and compression delay. simulation experiment on the arithmetic has been done by matlab

    針對無連接和面向連接的各種復雜網路環境下，通信頻帶資源緊張，音頻傳輸帶寬有限且復雜多變，而各種音頻數據又日益增多的局面，本文研究小波分析在信號處理方面的數學依據和在數據壓縮方面的實際意義，在前人不斷工作的基礎上，提出了一種優化小波包變換編碼方案用於音頻數據的壓縮演算法，兼考慮了編碼效率、多碼率和壓縮時延多個方面，並在matlab環境下做了模擬實驗，對各種音頻信號及多種小波函數做了模擬結果比較，實驗結果證明該演算法可以在一定計算復雜度下可以很好地改進壓縮效果，達到多碼率下實現實時編解碼的過程，在高速dsp晶元等硬體設備支持下，可以有效應用於實際復雜多變信源編碼。
  4. Thus, the vhdl is carried to make a design for the forenamed algorithms, and the design is validated by simulation

    因此，本文用vhdl語言實現了ca邊緣檢測演算法模型的基本內核設計，並通過時序模擬，進行了演算法的硬體設計與效果驗證。
  5. This thesis tries to update the cmdsr system to achieve the characters below : real - time, better robust, higher recognition rate, non - special - man. considering the disadvantages of traditional improved spectrum subtraction speech enhancement, this thesis proposes the theory of fuzzy spectrum subtraction based on the fuzzy theory and improved spectrum subtraction speech enhancement ; as for the difficulties of detecting the endpoint of speech signal, the thesis gives the table of initial and the improved parameters, with which we can confirm the endpoints of mandarin digit speech ; the thesis puts forward two - level digit real - time speech recognition system, the first level is based on discrete hidden markov model which is linear predictive coding cepstrum ( lpcc ) and difference linear predictive coding cepstrum ( dlpcc ), the second level is based on formant parameters ; as for the realization of hardware, the thesis depicts the realization of every part of cmdsr based on the tms320vc5402 in detail ; as for the development of software, the thesis gives the software design flow chart of cmdsr, simulates the basic theory with matlab language and gives the simulation results

    針對傳統的「改進譜相減法語音增強」參數設定單一、環境適應能力差的缺點，提出了一種利用模糊理論和「改進的譜相減法」結合的「模糊譜相減法語音增強」 ;針對語音信號端點檢測困難的特點，通過matlab模擬試驗，給出了能夠準確確定數碼語音端點的初始和改進參數表;提出了利用基於線性預測編碼倒譜參數和差分線性預測編碼倒譜參數相結合的離散隱含馬爾可夫模型進行第一級識別、利用共振峰參數進行第二級識別的兩級漢語數碼語音識別系統，在保證系統實時性的同時，實現連接漢語數碼語音識別系統識別率的提高;在硬體實現上，詳細闡述了基於tms320vc5402的連接漢語數碼語音識別系統各部分硬體設計;在軟體開發上，給出了連接漢語數碼語音識別的軟體設計各部分的流程圖，並對各部分進行了matlab模擬，並給出了模擬結果。
  6. Much of the hardware validation may be performed by the computer vendor

    計算機零售商是可以完成大多數的硬體驗證。
  7. My task is to write the code of hdlc / laps, vc - 12 virtual concatenation and sdram interface. the design has been verified on hardware

    本論文完成了上述的hdlc / laps協議處理、虛級聯處理、 sdram存取的設計及硬體驗證並通過了fpga實驗驗證。
  8. The main process includes following : system design, module design, function simulation, time simulation and hardware verification. the whole system is divided into several modules and each module is connected by signals, which based on the arithmetic of uart and the requirement of design. the module design is to design inner circuit structure of each module and uses verilog language to code the code

    系統設計是基於uart的實現演算法和設計指標要求，對系統劃分模塊以及各個模塊的信號連接;模塊設計是設計出每個模塊的功能，並用verilog一hdl語言編寫代碼來實現模塊功能;功能模擬和時序模擬使用的工具是以dence的nc _ veri109 ，首先對系統的每個模塊進行功能和時序模擬，模擬通過之後，將整個系統的代碼在外部的輸入埠加上激勵，對整個系統進行功能和時序模擬;硬體驗證是用fpga對系統進行了功能驗證。
  9. A widely distributed software package that supports the formal verification of distributed systems - is an example of temporal logic model checking for hardware verification

    一種支持分散式系統的正式驗證且廣泛發布的軟體包是用於硬體驗證的時態邏輯模型檢查的示例。
  10. This thesis presents a forward error correction ( fec ) algorithm and its circuit implementation, which is used in the wireless digital audio transmission system. also, an entire demo platform is built and error - correction ability of the system is tested based on this platform

    本文研究了一種應用於數字音頻無線傳輸系統中的前向糾錯（ fec ）演算法和相應的電路設計，搭建了一個硬體驗證平臺，並在驗證平臺上完成了電路的誤比特率測試。
  11. This thesis also gives a lot of explanation about these peripheral circuits and related algorithms

    本文對硬體驗證平臺的外圍電路和相關演算法也作了詳細介紹。
  12. This work has been validated in spartan ii series of fpga from xilinx company

    利用xilinx公司的spartanii系列的fpga晶元進行了靜態硬體驗證。
  13. In the part of platform designing, proper peripheral chips are chosen according to the audio signal format. and how to achieve channel synchronization in the receiving part is an important aspect of wireless transmission system. in order to solve this problem, three algorithms are used ; those are scramble / descramble, improved over - sampling, and frame synchronization protocol

    在硬體驗證平臺的設計部分，文章根據音頻信號的特點選擇了適當的外圍晶元，並且針對無線傳輸接收端的同步問題，採用了三種演算法來減少失步現象，即擾碼/解擾演算法，改進型的過采樣演算法，以及幀同步協議。
  14. A full implement scheme of soc software / hardware co - emulation system is given, including the communication protocol between software and hardware, data format, synchronous mechanism between software and hardware of different emulation modes

    給出了一套完整的soc軟硬體協同驗證系統的實現方案，其中包括了兩種不同驗證模式的軟硬體之間的通訊協議、數據格式、軟硬體驗證的同步機制等。
  15. These methods, with rigorous mathematical foundation, have mostly been developed for optimizing compilers and, more recently, for hardware and software verification

    這些方法有精確的數學基礎，曾經主要用於改良編譯器優化，近來也用於硬體和軟體驗證。
  16. A trial restoration can reveal hardware problems that do not appear with software verifications

    試驗性還原可以發現軟體驗證所不能發現的硬體問題。
  17. These are discussed in point no. 3 of validation of hardware

    對此的討論在硬體驗證第3部分。
  18. The fifth section, the whole process of fpga verification is introduced particually. the whole system is designed according to the design flow

    主要的步驟包括:系統設計，模塊設計，功能模擬、時序模擬和硬體驗證。
  19. At first. design and simulate on single module, secondly, on the whole system, at last verification using fpga

    先對各功能模塊進行設計、模擬、驗證，再對整個系統組合起來進行模擬、驗證，最後利用fpga進行硬體驗證。
  20. All the modules of risc mcu core were described with verilog hdl and synthesized with high - level synthesis eda tools. then the risc mcu was implemented in fpga device

    所有模塊都採用verilog硬體描述語言進行設計描述，使用eda工具進行功能模擬、綜合，並在fpga器件上完成了系統的硬體驗證。
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