碼字同步 的英文怎麼說

中文拼音 [mǎzìtóngbù]
碼字同步 英文
code word synchronization
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 字 : Ⅰ名詞1 （文字） character; word 2 （字音） pronunciation 3 （字體） form of a written or printed ...
  • 步 : Ⅰ名詞1 （步度; 腳步） pace; step 2 （階段） stage; step 3 （地步; 境地） condition; situation; st...
  1. In this thesis, firstly, we put forward a new algorithm of the synchronization of carrier reference phase, that is to use the curve synthesizing with the general digital carrier phase looper to have an estimation on carrier frequency within 10 ms so as to meet the need of meteor burst communication. we have done some simulations to get the performance of carrier frequency estimation using two modulation modes ( 16qam and 4 - qpsk ), and had some test on the carrier phase looper in conditions when using different baud rate transmission and when the baud tuning have windage

    我們對兩種正交調制方式（ 16qam和4 - qpsk ）進行了模擬工作並給出了模擬結果，同時討論了碼元同步定時誤差對鎖相環路工作的影響並根據流星通信中使用變速率傳輸時鎖相環路的載波同步性能進行了測試；然後在基於軟體無線電思想的數字處理平臺（該數字處理平臺實現了中頻數字化）上用dsp軟體完成了載波的相位跟蹤。
  2. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  3. The field of video signal processing is now undergoing a digital reform. the digital processing technique is clearly expatiated in this paper, such as a / d convert, anti - alias filter, clamp control, gain control, pll, synchronization circuit, color decoder, comb filters

    本文詳細敘述了視頻圖像的數字處理方法，重點介紹了視頻信號數字化技術、抗混疊濾波器、箝位、增益控制、鎖相技術、同步時鐘產生、電視信號亮色分離、彩色解碼等技術，這些關鍵技術為視頻信號的數字化處理提供了重要的基礎。
  4. A translation algorithm between code and index of synchronized variable length codes

    同步變長碼碼字和碼序號的互換演算法
  5. Digital audio - interface for non - linear pcm encoded audio bitstreams applying iec 60958 : burst - info

    數字音頻.應用iec 60958的非線性pcm編碼音頻位流用介面:色同步信息
  6. Digital audio - interface for non - linear pcm encoded audio bitstreams applying iec 60958 - part 2 : burst - info ; corrigendum 1

    數字音頻.應用iec 60958的非線性pcm編碼音頻位流的介面.第2部分:色同步信息.技術勘誤1
  7. This master ’ s degree thesis firstly introduces and discusses the principle of ofdm and the merged blue print for digital terrestrial television broadcasting in china, then proposes a scheme for the test platform of narrowband ldpc decoding efficiency based on fpga. this scheme includes techniques such as time - domain synchronization using pn and power estimation using pilots

    本論文首先介紹並討論了數字電視傳輸標準tds - ofdm的實現原理，對其中的一些關鍵問題做了詳細的分析，在此基礎上提出了一種基於fpga的窄帶ldpc解碼-誤碼測試平臺設計方案，即利用時域pn頭同步及頻域導頻進行功率估計的fpga設計。
  8. The digital base - band cdma transmitting and receiving scheme is put forward. the scheme uses a technique called as zero medium frequency without the need of pn codes synchronously are resumed

    提出了具有免偽碼同步恢復、免載波同步提取、免位同步的零中頻cdma數字基帶發送、接收方案。
  9. Secondly, some encryption algorithms are introduced, with the analysis and comparison for these encryption algorithms, the author designs an appropriate project to accomplish the end - to - end encryption. thirdly, this paper accomplish the design of an encryption scheme which combining the strongpoint of the rsa algorithm and the idea algorithm. the main process is as following : first, input the digital signal to the encryption device, and then the digital signal exclusive or with the keying sequence which is generated by key stream generator ( ksg ) and the ksg is based on the idea encrypting and deciphering algorithm, the secret key synchronization is also studied

    本課題主要研究的內容是數字集群通信系統加密機制的研究，首先介紹了數字集群通信系統的安全保密機制，講述了單向和雙向鑒權的過程、單呼和群呼的空中介面加密過程及其密鑰的選用和管理，特別介紹了端到端加密;然後介紹了幾種常用的加密演算法，通過分析其優劣，提出了端到端加密的解決方案;最後完成了基於rsa演算法和idea演算法的數字集群通信系統加密方案的設計，其具體過程為將經過數字信號送入加密器里，和以idea加密演算法為基礎設計的密碼流發生器（ ksg ）產生的密碼序列進行加解密運算，並且研究了此加密過程的密碼同步問題。
  10. The algorithm have the good one - way property, high sensitivity to initial values and good security due to the intrinsic characteristic of chaotic system and rijndael algorithm. the simulation experiment demonstrates the convenience and good hash performance ; 3 ) a new scheme of digital voice secure communication was proposed based on chaotic modulation without additional synchronization. the modulation sequence generated by chaotic logical mapping was used to encrypt the digital voice signal

    混沌系統和rijndael演算法的固有特點使該演算法具有較好的安全性、對初值有高度的敏感性以及較好的單向性能，並且易於實現，是一種有效的單向hash函數； 3 ）研究了一種無需同步的基於混沌調制的數字語音保密通信系統的方案，利用邏輯映射產生混沌調制序列，以該序列作為密碼對數字語音進行加密處理，為了更好的隱匿信號特徵，混沌調制在小波分解的基礎上，對不同的通道使用不同的參數進行，並借鑒混沌掩蓋對信息信號進行了限幅處理，使密文完全隨機化。
  11. This dissertation adopts a universal digital ds / dmpsk modulation and demodulation scheme which is based on fpga. this scheme adopts quadrature balanceable modulation, intermediate frequency sampling, digital matched filtering, delay differential demodulation techniques and so on. it directly processes the digital signals on intermediate frequency without down - conversion, and doesn ’ t need pseudo random codes synchronization and carrier wave extraction circuits

    本文採用了一種基於fpga的通用數字調制解調方案，該方案在調制端採用了正交平衡調制技術，在解調端採用了中頻帶通采樣、數字匹配濾波、延時差分解調等技術，直接在中頻上進行數字信號處理，不需要進行下變頻，也不需要增加額外的偽隨機碼同步捕獲和載波提取電路。
  12. Error code display in digits hexadecimal and led d0 - d7 binary display

    錯誤碼采十六進位碼數字顯示器與二進位碼led d0 - d7同步顯示
  13. The method of positioning synchronous control used pho toencoder as position measure and s5 - 100u plc is introduced in this paper. this system has advantages of high control accuracy, high reliability and low cost etc. in practice

    介紹了在全數字控制系統中利用光電碼盤作為位置檢測，利用s5 - 100u可編程序控制器完成位置同步控制的一種方法，並以推鋼機系統為例介紹此同步控制方法的硬體構成及軟體特點，通過實際應用表明，本系統具有控制精度高，可靠性強，成本低等優點。
  14. Abstract : the method of positioning synchronous control used pho toencoder as position measure and s5 - 100u plc is introduced in this paper. this system has advantages of high control accuracy, high reliability and low cost etc. in practice

    文摘:介紹了在全數字控制系統中利用光電碼盤作為位置檢測，利用s5 - 100u可編程序控制器完成位置同步控制的一種方法，並以推鋼機系統為例介紹此同步控制方法的硬體構成及軟體特點，通過實際應用表明，本系統具有控制精度高，可靠性強，成本低等優點。
  15. The input data of the multiplexing adopts 8 channels with the speed of 2mb / s, and those of the last two channels are " 0 " and " 1 " respectively, in order to improve the transimision effeciency and deminish the complexity of encode and electronic circuit concerned, furthermore, it makes the synchronous signal acquisition more easier

    數字復接中採用八路2m口數據輸入，其中后兩路採用直接輸入「 0 」碼或「 1 」碼的方法，提高了信息傳輸的有效性，便於提取幀同步碼，降低了編譯碼過程的復雜性，同時也降低了系統的電路復雜程度。
  16. The clock obtaining practical circuit in approximately synchronization and clock circuit about symbol synchronization are designed ( realized one circuit ) ; the three controlling circuits with fast and low clock in code speed adjust technique are designed

    在此基礎上設計了基於scc準同步的一種時鐘恢復實現電路和兩種字元型起止式同步電路（實現了一種） 。設計了正碼速調整技術中快慢時鐘的三種控制電路。
  17. This system is based on two altera ’ s statixii series fpga chips ep2s180f1020c5, and the tunner dtt7579 and the chip ad9433, together composed the main hardware platform. the hardware description system running on the fpga is the core of digital down converted sysgtem, synchronization system, estimation and equalization of channel system, 3780 - point fft ofdm demodulation system, frequency equalization system and ldpc decoding

    以兩片altera公司的stratixii系列ep2s180f1020c5級聯為基礎構建了系統主硬體處理平臺，結合湯姆遜公司的調諧器dtt7579以及ad9433組成了系統的硬體構架fpga可描述硬體系統的核心任務包括數字下變頻，同步和通道均衡與估計， 3780點fftofdm解調，頻域均衡， ldpc解碼。
  18. Digital phase lock loop is used in this section to synchronize to an incoming serial data stream

    數據接收解碼模塊中使用了數字鎖相環技術從輸入數據碼流中提取出同步時鐘信號。
  19. Owing to its proximity to the mainland, coupled with tariffs - free arrangement under cepa, hong kong manufactures have gained a head - start in entering the mainland market. moreover, the mainland is developing its own standards such as avs, wapi, td - scdma, and hdtv standards

    此外，內地正訂立多項國家標準，例如數字音視頻編解碼技術標準（ avs ） 、無線局域網加密標準（ wapi ） 、時分同步碼分多址接入標準（ td - scdma ）及高清晰度電視標準（ hdtv ）等。
  20. Abstract : ： a technique for carriersynchronization of a digital modem is studied and the results of computer simulations are given. through comp arison of twokinds of phase estimator systems, it is shown that the combination of phase signal decision process and signal decoding processwill improve system performances obviously

    文摘:分析了數字數據機載波同步技術，提供了計算機模擬測試的結果，並通過對兩種不同鑒相器系統的性能比較，說明了把信號相位判斷過程與信號解碼過程結合，可使系統的性能得到明顯改善。
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